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IDT7026L35JGI

Description
Dual-Port SRAM, 16KX16, 35ns, CMOS, PQCC84, PLASTIC, LCC-84
Categorystorage    storage   
File Size172KB,18 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

IDT7026L35JGI Overview

Dual-Port SRAM, 16KX16, 35ns, CMOS, PQCC84, PLASTIC, LCC-84

IDT7026L35JGI Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeLCC
package instructionQCCJ,
Contacts84
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time35 ns
Other features16K X 16 DUAL PORT SRAM
JESD-30 codeS-PQCC-J84
JESD-609 codee3
length29.3116 mm
memory density262144 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Number of functions1
Number of terminals84
word count16384 words
character code16000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize16KX16
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width29.3116 mm
Base Number Matches1
HIGH-SPEED
16K X 16 DUAL-PORT
STATIC RAM
IDT7026S/L
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
– Military: 20/25/35/55ns (max.)
Low-power operation
– IDT7026S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7026L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multi-
plexed bus compatibility
IDT7026 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master,
M/S = L for
BUSY
input on Slave
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA and 84-pin PLCC
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
BUSY
L
A
13L
A
0L
(1,2)
I/O
Control
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
R
A
13R
A
0R
(1,2)
Address
Decoder
14
MEMORY
ARRAY
14
Address
Decoder
CE
L
ARBITRATION
SEMAPHORE
LOGIC
CE
R
SEM
L
M/S
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs are non-tri-stated push-pull.
SEM
R
2939 drw 01
DECEMBER 2002
1
DSC 2939/12
©2001 Integrated Device Technology, Inc.
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