Part Number 440GX
Revision 1.01 – November 1, 2004
440GX
Features
Data Sheet
Power PC 440GX Embedded Processor
• PowerPC
®
440 processor core operating up to
800MHz with 32KB I- and D-caches (with parity
checking)
• On-chip 256KB SRAM configurable as L2 Code
store or Ethernet Packet store memory
• Selectable processor:bus clock ratios (Refer to
the Clocking chapter in the
PPC440GX
Embedded Processor User’s Manual
for details)
• Double Data Rate (DDR) Synchronous DRAM
(SDRAM) interface operating up to 166MHz
• External Peripheral Bus (32 bits) for up to eight
devices with external mastering
• DMA support for external peripherals, internal
UART and memory
• PCI-X V1.0a interface (32 or 64 bits, up to
133MHz) with support for conventional PCI V2.3
• Two Ethernet 10/100/1000Mbps half- or full-
duplex interfaces. Operational modes supported
are SMII, GMII, RGMII, TBI and RTBI.
• TCP/IP Acceleration Hardware (TAH) provided for
10/100/1000 Mbps ports that performs checksum
processing, TCP segmentation, and includes
support for jumbo frames
• Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are MII,
RMII, and SMII.
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
• I2O Messaging unit for message transfer between
the CPU and PCI-X
• Programmable General Purpose Timers (GPT)
• Two serial ports (16750 compatible UART)
• Two IIC interfaces
• General Purpose I/O (GPIO) interface available
• JTAG interface for board level testing
• Processor can boot from PCI memory
• Available in ceramic and plastic packages
Description
Designed specifically to address high-end embedded
applications, the PowerPC 440GX (PPC440GX)
provides a high-performance, low power solution that
interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation.
This chip contains a high-performance RISC
processor core, DDR SDRAM controller, configurable
256KB SRAM to be used as L2 cache or software-
controlled on-chip memory, PCI-X bus interface,
Gigabit Ethernet interfaces, TCP/IP acceleration
hardware, I2O messaging unit, control for external
ROM and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general
purpose I/O.
Technology: CMOS Cu-11, 0.13µm , 6-layer metal
Packages: 25mm, 552-ball Ceramic Ball Grid Array
(CBGA) or Plastic Ball Grid Array (PBGA)
Power (estimated): Less than:
4W typical @533MHz
5W typical @667MHz
6W typical @800MHz (estimated)
Supply voltages required: 3.3V, 2.5V, 1.5V
AMCC
1
440GX – Power PC 440GX Embedded Processor
Revision 1.01 – November 1, 2004
Data Sheet
Contents
Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DDR SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PLB Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I2O Messaging Unit (IMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Heat Sink Mounting Information (Ceramic Package Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2
AMCC
Revision 1.01 – November 1, 2004
Data Sheet
Figures
440GX – Power PC 440GX Embedded Processor
PPC440GX Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
25mm, 552-Ball CBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
25mm, 552-Ball FC-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Heat Sink Attached With Spring Clip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Heat Sink Attached With Adhesive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DDR SDRAM Signal Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DDR SDRAM MemClkOut0 and Read Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DDR SDRAM Read Cycle Timing—Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
DDR SDRAM Read Cycle Timing—Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
DDR SDRAM Read Cycle Timing—Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Tables
System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O Specifications—500MHz–800MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I/O Timing—DDR SDRAM T
DS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I/O Timing—DDR SDRAM T
SK
, T
SA
, and T
HA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I/O Timing—DDR SDRAM T
SD
and T
HD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O Timing—DDR SDRAM T
SIN
and T
DIN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
AMCC
3
440GX – Power PC 440GX Embedded Processor
Revision 1.01 – November 1, 2004
Data Sheet
Ordering and PVR Information
For information on the availability of the following parts, contact your local AMCC sales office.
Product
Name
PPC440GX
PPC440GX
PPC440GX
PPC440GX
PPC440GX
Notes:
Order Part Number
PPC440GX-3CC533C
PPC440GX-3CC533E
PPC440GX-3CC667C
PPC440GX-3CC800C
PPC440GX-3FC533C
Processor
Frequency
533MHz
533MHz
667MHz
800MHz
533MHz
Package
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 PBGA
Rev
Level
C
C
C
C
C
PVR Value
0x51B21892
0x51B21892
0x51B21892
0x51B21892
0x51B21892
JTAG ID
0x32054049
0x32054049
0x32054049
0x32054049
0x32054049
1. These part numbers are prototype parts that are intended for evaluation purposes only. Only revision level C parts are available for pro-
duction use.
Each part number contains a revision code. This is the die mask revision number and is included in the part
number for identification purposes only.
The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain
information that uniquely identifies the part. Refer to the
PPC440GX User’s Manual
for details on accessing these
registers.
Order Part Number Key
PPC440GX-3CC800Ex
Shipping Package:
Blank = Tray
Part Number
Case Temperature Range
C = -40°C to +85°C
E = -40°C to +105°C
Grade 3 Reliability
Package
C = Ceramic
F = Plastic
Processor Speed
Revision Level
4
AMCC
Revision 1.01 – November 1, 2004
Data Sheet
PPC440GX Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Timers
MMU
63 internal
18 external
Power
Mgmt
440GX – Power PC 440GX Embedded Processor
DCRs
PPC440
Processor Core
JTAG
32KB
D-Cache
Trace
32KB
I-Cache
Arb
DCR Bus
GP
Timers
GPIO
IIC
x2
UART
x2
On-chip Peripheral Bus (OPB)
L2 Controller
SRAM
256KB
DMA
Controller
(4-Channel)
OPB
Bridge
Processor Local Bus (PLB)
TAH
10/100/
1000 x2
External
External
Bus Master
Bus
Controller Controller
83MHz max
32-bit addr
32-bit data
MAL
10/100
x2
Ethernet
I2O
Messaging
PCI-X
Bridge
DDR SDRAM
Controller
RGMII
Bridge
ZMII
Bridge
1 MII
or
2 RMII
or
133MHz max 166MHz max
32/64-bit data 13-bit addr
32/64-bit data
1 GMII
or
2
RGMII
or
1 TBI
The PPC440GX is designed using the IBM
®
Microelectronics Blue Logic
™
methodology in which major functional
blocks are integrated together to create an application-specific product (ASIC). This approach provides a
consistent way to create complex ASICs using IBM CoreConnect Bus
™
Architecture.
Note:
IBM CoreConnect buses provide:
• 128-bit PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data paths (5.2GB/s total)
• 32-bit OPB interfaces up to 83.33MHz, 333MB/s
Address Maps
The PPC440GX incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various address regions which the processor can access. The
second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running
on the PPC440GX processor through the use of
mtdcr
and
mfdcr
instructions.
AMCC
5
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