2. Pin 1: NC - No Connection IDT72402,OE - IDT72404
CERPACK
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Terminal Voltage
with Respect
to GND
Operating Temp.
Temperature
Under Bias
Storage Temp.
DC Output
Current
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
CC
GND
V
IH
V
IL(1)
Parameter
Mil. Supply Voltage
Com'l. Supply Voltage
Supply Voltage
Input High Voltage
Input High Voltage
Min.
4.5
4.5
0
2.0
—
Typ.
5.0
5.0
0
—
—
Max. Unit
5.5
5.5
0
—
0.8
V
V
V
V
V
2747 tbl 02
T
A
T
BIAS
T
STG
I
OUT
0 to +70
–55 to +125
–55 to +125
50
–55 to +125
–65 to +135
–65 to +150
50
°C
°C
°C
mA
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
NOTE:
2747 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
5
7
Unit
pF
pF
2747 tbl 03
NOTE:
1. This parameter is sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5.0V
±
10%, T
A
= –55°C to +125°C)
Symbol
I
IL
I
IH
V
OL
V
OH
I
OS(1)
I
HZ
I
LZ
I
CC(2,3)
Parameter
Low-Level Input Current
High-Level Input Current
Low-Level Output Voltage
High-Level Output Voltage
Output Short-Circuit Current
Off-State Output Current
(IDT72403 and IDT72404)
Supply Current
Test Conditions
V
CC
= Max., GND
≤
V
I
≤
V
CC
V
CC
= Max., GND
≤
V
I
≤
V
CC
V
CC
= Min., I
OL
= 8mA
V
CC
= Min., I
OH
= -4mA
V
CC
= Max., V
O
= GND
V
CC
= Max., V
O
= 2.4V
V
CC
= Max., V
O
= 0.4V
V
CC
= Max., f = 10MHz
Com'l.
Military
Min.
–10
—
—
2.4
–20
—
–20
—
—
Max.
—
10
0.4
—
–110
20
—
35
45
Unit
µA
µA
V
V
mA
µA
µA
mA
mA
04
NOTES:
2747 tbl
1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested.
2. I
CC
measurements are made with outputs open. OE is HIGH for IDT72403/72404.
3 For frequencies greater than 10MHZ, I
CC
= 35mA + (1.5mA x [f - 10MHz]) commercial, and I
CC
= 45mA + (1.5mA x [f - 10MHz]) military.
5.01
2
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONDITIONS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5.0V
±
10%, T
A
= –55°C to +125°C)
Commercial
IDT72401L45
IDT72402L45
IDT72403L45
IDT72404L45
Min.
Max.
9
11
0
13
9
11
20
10
3
13
0
—
—
—
—
—
—
—
—
—
—
—
IDT72401L35
IDT72402L35
IDT72403L35
IDT72404L35
Min.
Max.
9
17
0
15
9
17
25
10
3
15
0
—
—
—
—
—
—
—
—
—
—
—
Military and Commercial
IDT72401L25 IDT72401L15
IDT72402L25 IDT72402L15
IDT72403L25 IDT72403L15
IDT72404L25 IDT72404L15
Min.
Max.
Min.
Max.
11
24
0
20
11
24
25
10
5
20
0
—
—
—
—
—
—
—
—
—
—
—
11
25
0
30
11
25
25
25
5
30
0
—
—
—
—
—
—
—
—
—
—
—
IDT72401L10
IDT72402L10
IDT72403L10
IDT72404L10
Min.
Max.
11
30
0
40
11
25
30
35
5
30
0
—
—
—
—
—
—
—
—
—
—
—
Symbol
t
SIH
t
SIL
t
IDS
t
IDH
t
SOH(1)
t
SOL
t
MRW
t
MRS
t
SIR
t
HIR
t
SOR(4)
(1)
Parameters
Shift in HIGH Time
Shift in LOW TIme
Input Data Set-up
Input Data Hold Time
Shift Out HIGH Time
Shift Out LOW Time
Master Reset Pulse
Master Reset Pulse to SI
Data Set-up to IR
Data Hold from IR
Data Set-up to OR HIGH
FIgure
2
2
2
2
5
5
8
8
4
4
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2747 tbl 05
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5.0V
±
10%, T
A
= –55°C to +125°C)
Commercial
IDT72401L45
IDT72402L45
IDT72403L45
IDT72404L45
Min.
Max.
—
—
—
—
—
—
5
—
—
—
—
—
—
—
9
9
45
18
18
45
18
19
—
19
30
25
25
20
12
12
—
—
IDT72401L35
IDT72402L35
IDT72403L35
IDT72404L35
Min.
Max.
—
—
—
—
—
—
5
—
—
—
—
—
—
—
9
9
35
18
20
35
18
20
—
20
34
28
28
20
15
12
—
—
Military and Commercial
IDT72401L25 IDT72401L15
IDT72402L25 IDT72402L15
IDT72403L25 IDT72403L15
IDT72404L25 IDT72404L15
Min.
Max.
Min.
Max.
—
—
—
—
—
—
5
—
—
—
—
—
—
—
11
11
25
21
28
25
19
34
—
34
40
35
35
25
20
15
—
—
—
—
—
—
—
—
5
—
—
—
—
—
—
—
11
11
15
35
40
15
35
40
—
40
65
35
35
35
30
25
—
—
IDT72401L10
IDT72402L10
IDT72403L10
IDT72404L10
Min.
Max.
—
—
—
—
—
—
5
—
—
—
—
—
—
—
11
11
10
40
45
10
40
55
—
55
65
40
40
40
35
30
—
—
Symbol
t
IN
t
IRL(1)
t
IRH(1)
t
OUT
t
ORL
(1)
(1)
Parameters
Shift In Rate
Shift In to Input Ready LOW
Shift In to Input Ready HIGH
Shift Out Rate
Shift Out to Output Ready LOW
Shift Out to Output Ready HIGH
Output Data Hold (Previous Word)
Output Data Shift (Next Word)
Data Throughput or "Fall-Through"
Master Reset to OR LOW
Master Reset to IR HIGH
Master Reset to Data Output LOW
Output Valid from OE LOW
Output High-Z from OE HIGH
Input Ready Pulse HIGH
Ouput Ready Pulse HIGH
FIgure
2
2
2
5
5
5
5
5
4, 7
8
8
8
9
9
4
7
Unit
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
ORH
t
ODH
t
ODS
t
PT
t
MRORL
t
MRIRH
t
MRQ
t
OOE(3)
t
HZOE(3,4)
t
IPH(2,4)
t
OPH(2,4)
NOTES:
2747 tbl 06
1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding
and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between V
CC
and GND with very short lead length is recommended.
2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of
like speed grades.
3. IDT72403 and IDT72404 only.
4. Guaranteed by design but not currently tested.
5.01
3
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2747 tbl 07
5V
560
Ω
OUTPUT
1.1K
Ω
30pF*
2747 drw 06
ALL INPUT PULSES:
3.0V
GND
or equivalent
circuit
90%
10%
90%
10%
<3ns
<3ns
2747 drw 05
Figure 1. AC Test Load
*Including scope and jig
SIGNAL DESCRIPTIONS
INPUTS:
DATA INPUT (D
0-3
,
4
)
OUTPUTS:
DATA OUTPUT (Q
0-3
,
4
)
Data Output lines. The IDT72401 and IDT72403 have a 4-
bit data output. The IDT72402 and IDT72404 have a 5-bit data
output.
Data input lines. The IDT72401 and IDT72403 have a 4-bit
data input. The IDT72402 and IDT72404 have a 5-bit data
input.
FUNCTIONAL DESCRIPTION
These 64 x 4 and 64 x 5 FIFOs are designed using a dual
port RAM architecture as opposed to the traditional shift
register approach. This FIFO architecture has a write pointer,
a read pointer and control logic, which allow simultaneous
read and write operations. The write pointer is incremented by
the falling edge of the Shift In (Sl) control; the read pointer is
incremented by the falling edge of the Shift Out (SO). The
Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is
valid data on the output. Output Enable (OE) provides the
capability of three-stating the FIFO outputs.
FIFO Reset
The FIFO must be reset upon power up using the Master
Reset (MR) signal. This causes the FlFO to enter an empty
state, signified by Output Ready (OR) being LOW and Input
Ready (IR) being HIGH. In this state, the data outputs (Q
0-3,
4
) will be LOW.
Data Input
Data is shifted in on the LOW-to-HlGH transition of Shift In
(Sl). This loads input data into the first word location of the
FIFO and causes Input Ready to go LOW. On the HlGH-to-
LOW transition of Shift In, the write pointer is moved to the next
word position and Input Ready (IR) goes HIGH, indicating the
readiness to accept new data. If the FIFO is full, Input Ready
will remain LOW until a word of data is shifted out.
CONTROLS:
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When
SI is HIGH, data can be written to the FIFO via the D
0-3, 4
lines.
SHIFT OUT (SO)
Shift Out controls the output of data of the FIFO. When SO
is HIGH, data can be read from the FIFO via the Data Output
(Q
0-3, 4
) lines.
MASTER RESET (MR)
Master Reset clears the FIFO of any data stored within.
Upon power up, the FIFO should be cleared with a Master
Reset. Master Reset is active LOW.
INPUT READY (IR)
When Input Ready is HIGH, the FIFO is ready for new input
data to be written to it. When IR is LOW the FIFO is unavailable
for new input data. Input Ready is also used to cascade many
FlFOs together, as shown in Figures 10 and 11 in the Applica-
tions section.
OUTPUT READY (OR)
When Output Ready is HIGH, the output (Q
0-3, 4
) contains
valid data. When OR is LOW, the FIFO is unavailable for new
output data. Output Ready is also used to cascade many
FlFOs together, as shown in Figures 10 and 11.
OUTPUT ENABLE (OE) (IDT72403 AND IDT72404 ONLY)
Output enable is used to read FIFO data onto a bus. Output
Enable is active LOW.
5.01
4
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Data Output
Data is shifted out on the HlGH-to-LOW transition of Shift
Out (SO). This causes the internal read pointer to be
advanced to the next word location. If data is present, valid
data will appear on the outputs and Output Ready (OR) will
go HIGH. If data is not present, Output Ready will stay
LOW indicating the FIFO is empty. The last valid word read
from the FIFO will remain at the FlFOs output when it is empty.
When the FIFO is not empty, Output Ready (OR) goes LOW
on the LOW-to-HIGH transition of Shift Out. Previous data
remains on the output until the HIGH-to-LOW transition of
Shift Out (SO).
Fall-Through Mode
The FIFO operates in a fall-through mode when data gets
shifted into an empty FIFO. After a fall-through delay the data
propagates to the output. When the data reaches the output,
the Output Ready (OR) goes HIGH. Fall-through mode also
occurs when the FIFO is completely full. When data is shifted
out of the full FIFO, a location is available for new data. After
a fall-through delay, the Input Ready goes HIGH. If Shift In is
HIGH, the new data can be written to the FIFO.
Since these FlFOs are based on an internal dual-port RAM
architecture with separate read and write pointers, the fall-
through time (tPT) is one cycle long. A word may be written
into the FIFO on a clock cycle and can be accessed on the next
clock cycle.
TIMING DIAGRAMS
1/f
IN
SHIFT IN
t
SIH
t
SIL
t
IRH
INPUT READY
t
IDH
INPUT DATA
t
IDS
Figure 2. Input Timing
2747 drw 07
1/f
IN
t
IRL
(7)
SHIFT IN
(1)
(2)
(4)
(5)
INPUT READY
(3)
(6)
INPUT DATA
STABLE DATA
2747 drw 08
NOTES:
1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied.
2. Input Data is loaded into the first word.
3. Input Ready goes LOW indicating the first word is full.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full then the Input Ready remains LOW.
7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4).
Figure 3. The Mechanism of Shifting Data Into the FIFO
京公网安备 11010802033920号
EEWORLD
