SM3EG5
ULTRA MINIATURE
STRATUM 3E MODULE
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Application
The SM3EG5 Timing Module is a
complete system clock module for
Stratum 3E timing applications and
conforms to GR-1244-CORE (Issue
2), GR-253-CORE (Issue 3) and ITU-T
G.812 (Option 3). Applications include
shared port adapters, data digital
cross connects, ADM’s, DSLAM’s,
multiservice platforms, switches and
routers in TDM, SDH and SONET
environments.
The SM3EG5 Timing Module
guarantees full Stratum 3E compliance
with a minimum of effort and cost
in the smallest complete package
available.
This product is ROHS-5 compliant.
ROHS-5 indicates that this product is
ROHS compliant except for lead from
those manufacturers wishing to take
the lead exemption.
Features
Small Package Size,
2.05 x 1.25 x 0.75 inches
Eight Auto Select Input
References,
8 kHz - 77.76 MHz
Phase Buildout
Better than 1ppb initial Hold
Over offset
Frequency Qualification and Loss
of Reference detection for each
input
Master/Slave Operation with
Phase Adjustment
Manual/Autonomous Operation
Bi-Directional SPI Port Control
and Status Reporting
Three CMOS Frequency Outputs
- Output1 from 1.544 - 77.76MHz,
M/S_Out@8KHz, BITS @2.048
MHz or 1.544 MHz
3.3V operation
ROHS-5 Compliant
Bulletin
Page
Revision
Date
Issued By
TM098
1 of 36
01
09 July 2010
BBell
General Description
The SM3EG5 timing module provides a clock output that meets or exceeds Stratum 3E specifications given in GR-1244-CORE
(Issue 2), GR-253-CORE (Issue 3) and ITU-T G.812 (option 3). The SM3EG5 features eight reference inputs. Each input will auto-detect
the following reference frequencies: 8 kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz and
77.76 MHz.
The SM3EG5 timing module can be configured during production to produce an output up to 77.76MHz. This output is derived
from an onboard VCXO and must be specified when ordering. The second output is a BITS output selectable for either 1.544 or 2.048
MHz. The master/slave output is 8KHz. The user communicates with the SM3EG5 module through a SPI port. The user controls the
SM3EG5 operation by writing to the appropriate registers. The user can also enable or disable SPI operation through a SPI_Enable pin.
The SM3EG5 offers a wide range of options for the system designer. The bandwidth is SPI Port-selectable from 0.00084 Hz to
1.6 Hz. 0.0016 Hz is the recommended operational bandwidth for Stratum 3E applications. The 8 kHz output has an adjustable pulse
width. The pull-in range is also adjustable to establish the desired reference frequency rejection limits. A Free Run frequency calibra-
tion value can be written to the module to provide a high degree of accuracy in the free run mode. The reference frequency for any
given reference input is automatically detected. A wealth of status information is available through the SPI Port registers. The user also
has a choice between autonomous or full manual control operation.
In manual mode, the user controls the module operating modes Free Run, Hold Over or locked to a specific reference. If the cho-
sen reference is unavailable or disqualified the module automatically enters Hold Over.
In autonomous control mode, operational mode selection occurs automatically based on reference priority and qualification status.
When the active reference becomes disqualified, the module will switch to another qualified reference. If none is available, it will switch
to Hold Over. In the revertive mode the module will seek to acquire the highest priority qualified reference. In the non-revertive mode
the module will not return to the previous reference even after it is re-qualified unless there are no other qualified references.
Switching between references is hitless. Likewise, the output frequency slew rate is minimized during any change of operating
mode, including entry into and return from Free Run or Hold Over to protect traffic from transient-induced bit errors.
Reference Status information and the operating mode information is accessed through status registers. The module will set the
Interrupt pin (SPI_INT) low to indicate a status change.
Free Run operation guarantees an output within 4.6ppm of nominal frequency and Hold Over operation guarantees the output fre-
quency will not change by more than 0.012ppm during the first 24 hours. Frequency accuracy is based on a precision oven to provide
the stabilty required for Stratum 3E compliance.
The SM3EG5 can be programmed to startup in any mode or bandwidth. The module may even be programmed to operate in an a
fully autonomous mode with no further configuration required.
The module operates on 3.3V ± 5% with a typical power drain of less than 3W at turn on, dropping to approximately 1W @ room
temperature after warming up. The module operates over the 0° to 70° C commercial temperature range.
Phase buildout can be enabled or disabled by means of the SPI port.
Functional Block Diagram
Figure 1
TRST
TCK
TDO
TDI
TMS
M/S REF
Ref 1 - 8
Reset
MASTER SELECT
T1/E1
SPI_ENBL
SPI_Clk
SPI_In
SPI_Out
SPI_INT
Bus Interface
Reference Priority,
Revertivity and Mask
Table
8
Control
Mode
Reference
Selection
DPLL
APLL
LOS
LOL
Hold_Good
Reference Input Monitor
OCXO
EEPROM
DAC
VCXO
Output 1
M/S_OUT
BITS_Clk
SM3EG5 Data Sheet #:
TM098
Page 2
of
36
Rev:
01
Date:
07/09/10
© Copyright 2010 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Specifications for Ultra Miniature Stratum 3E
Table 1
Parameter
Voltage
Power
Reference Frequency 1 - 8
CMOS Output Frequency #1
M/S_Out
BITS_Clk
Master/Slave I/O
Free Run Accuracy
Hold Over Accuracy
Hold Over Stability
Dimensions
Specification
3.3V ± 5%
3W Maximum during start up, 1.5W Typical @ room temperature
8 kHz - 77.76 MHz (Determined by customer’s application)
8 kHz - 77.76 MHz
8 kHz
1.544/2.048 MHz (Selectable)
8 kHz
4.6 ppm
0.001 ppm
0.012 ppm for the first 24 hours
2.05 x 1.25 x 0.75 inches (52.07 x 31.75 x 19.05 mm)
Pin Description
Table 2
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O
O
O
I
I
I
I
I
O
O
O
I
O
I
I
I
I
O
O
I
Pin Name
LOS
LOL
M/S REF
REF1
REF2
REF3
REF4
TDI
TMS
TRST
BITS_CLK
M/S_OUT
OUTPUT1
VPP
REF5
REF6
REF8
REF7
TDI
VPN
T 1/E1
HOLD_GOOD
TDO
TCK
GND
SPI_CLK
SPI_IN
VCC
SPI_ENBL
RESET
SPI_OUT
SPI_INT
MASTER SELECT
Pin Description
Alarm Output - Loss of Active Reference Signal
Alarm Output - Loss of Lock
Master/Slave Reference Input
Reference Input 1 – 8 kHz to 77.76 MHz auto detected
Reference Input 2 – 8 kHz to 77.76 MHz auto detected
Reference Input 3 – 8 kHz to 77.76 MHz auto detected
Reference Input 4 – 8 kHz to 77.76 MHz auto detected
JTAG TDI pin
JTAG TMS pin
JTAG TRST pin
1.544 or 2.048 MHz output selected by pin 14
Master/Slave 8 kHz output
Synchronous Primary Output
Positive Programming Supply Pin. During normal operation, it is
recommended to float this pin.
Reference Input 5 – 8 kHz to 77.76 MHz auto detected
Reference Input 6 – 8 kHz to 77.76 MHz auto detected
Reference Input 8 – 8 kHz to 77.76 MHz auto detected
Reference Input 7 – 8 kHz to 77.76 MHz auto detected
JTAG TDI pin
Negative Programming Supply Pin. During normal operation, it is
recommended to float this pin.
BITS_CLK select input – 1=1.544 MHz, 0=2.-48 MHz, 4.7k Ohm Pull-up
Holdover Good Output Flag – 1=Holdover Available
JTAG TDO pin
JTAG TCK pin
Module Ground
SPI Port Clock input
SPI Port Data input
3.3 Vdc VCC Supply Input
SPI Port Enable input – Active Low, 4.7k Ohm Pull-up
Module Reset – Active Low, 4.7k Ohm Pull-up
SPI Port Data Output
SPI Port Interrupt Output
Master/Slave select input – 1=Master, 0=Slave
SM3EG5 Data Sheet #:
TM098
Page 3
of
36
Rev:
01
Date:
07/09/10
© Copyright 2010 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Pin Diagram
Figure 2
SM3E
LOS
LOL
M/S REF
REF1
REF2
REF3
REF4
TDI
TMS
TRST
BITS_CLK
M/S_OUT
OUTPUT1
VPP
REF5
REF6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
MASTER SELECT
SPI_INT
SPI_OUT
RESET
SPI_ENBL
Vcc
SPI_IN
SPI_CLK
GND
TCK
TDO
HOLD_GOOD
T1/E1
VPN
REF7
REF8
(TOP VIEW)
26
25
24
23
22
21
20
19
18
17
Register Map
Table 3
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x0f
Reg Name
Chip_ID_Low
Chip_ID_High
Chip_Revision
Bandwidth_PBO
Ctl_Mode
Op_Mode
Max_Pullin_Range
M/S Input_Activity
Ref_Activity
Ref_Pullin_Sts
Ref_Qualified
Ref_Mask
Ref_Available
Ref_Rev_Delay
Phase_Offset
Calibration
Description
Low byte of chip ID
High byte of chip ID
Chip revision number
Bandwidth & Phase Build-Out option
Manual or automatic selection of Op_Mode,BITS clock output frequency
indication, and frame/multi-frame sync pulse width mode control
Master Free Run, Locked, or Hold Over mode, or Slave mode
Maximum pull-in range in 0.1 ppm units
Cross Reference activity
Activities of 8 reference inputs
In or out of pull-in range of 8 reference inputs
Qualification of 8 reference inputs
Availability mask for 8 reference inputs
Availability of 8 reference inputs
Reference reversion delay time, 0 - 255 minutes
Phase offset between M/S REF & M/S Output (for the Slave in
M/S operation) in 250ps resolution
Local oscillator digital calibration in 0.05 ppm resolution
Type
R
R
R
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R
R/W
R/W
R/W
SM3EG5 Data Sheet #:
TM098
Page 4
of
36
Rev:
01
Date:
07/09/10
© Copyright 2010 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Register Map Continued
Table 3
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
0x1f
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x30
0x31
0x32
0x33
0x35
0x37
0x38
0x39
Fr_Pulse_Width
DPLL_Status
Intr_Event
Intr_Enable
Ref1_Frq_Offset
Ref2_Frq_Offset
Ref3_Frq_Offset
Ref4_Frq_Offset
Ref5_Frq_Offset
Ref6_Frq_Offset
Ref7_Frq_Offset
Ref8_Frq_Offset
Ref1_Frq_Priority
Ref2_Frq_Priority
Ref3_Frq_Priority
Ref4_Frq_Priority
Ref5_Frq_Priority
Ref6_Frq_Priority
Ref7_Frq_Priority
Ref8_Frq_Priority
FreeRun Priority
History_Policy
History_CMD
HoldOver_Time
Cfgdata
Cfgctr_Lo
Cfgctr_Hi
Chksum
EE_Wrt_Mode
EE_Cmd
EE_Page_Num
EE_FIFO_Port
Frame sync pulse width
Digital Phase Locked Loop status
Interrupt events
Enable individual interrupt events
Ref1 frequency offset in 0.2 ppm resolution
Ref2 frequency offset in 0.2 ppm resolution
Ref3 frequency offset in 0.2 ppm resolution
Ref4 frequency offset in 0.2 ppm resolution
Ref5 frequency offset in 0.2 ppm resolution
Ref6 frequency offset in 0.2 ppm resolution
Ref7 frequency offset in 0.2 ppm resolution
Ref8 frequency offset in 0.2 ppm resolution
Ref1 frequency and priority
Ref2 frequency and priority
Ref3 frequency and priority
Ref4 frequency and priority
Ref5 frequency and priority
Ref6 frequency and priority
Ref7 frequency and priority
Ref8 frequency and priority
Control and Priority for designation of Free Run as a reference
Sets policy for Hold Over history accumulation
Save, restore and flush comands for Hold Over history
Indicates the time since entering Hold Over state
Configuration data write register
Configuration data write counter, low byte
Configuration data write counter, high byte
Configuration data checksum pass/fail indicator
Disables/Enables writing to the external EEPROM
Read/Write command & ready indication register for ext. EEPROM access
Page number for external EEPROM access
Read/Write data for external EEPROM access
R/W
R
R
R/W
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R
R
R/W
R/W
R/W
R/W
SM3EG5 Data Sheet #:
TM098
Page 5
of
36
Rev:
01
Date:
07/09/10
© Copyright 2010 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
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