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Free
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Options
Available!
ispLSI 2096/A
In-System Programmable High Density PLD
Functional Block Diagram
Output Routing Pool (ORP)
Output Routing Pool (ORP)
®
Features
• ENHANCEMENTS
— ispLSI 2096A is Fully Form and Function Compatible
to the ispLSI 2096, with Identical Timing
Specifcations and Packaging
— ispLSI 2096A is Built on an Advanced 0.35 Micron
E
2
CMOS
®
Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
4000 PLD Gates
96 I/O Pins, Six Dedicated Inputs
96 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E CMOS TECHNOLOGY
—
—
—
—
—
—
—
2
®
C7
A0
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool (ORP)
S
N
B2
B3
B6
Output Routing Pool (ORP)
B7
Select devices have been discontinued.
See Ordering Information section for product status.
D Q
A1
—
—
—
—
—
A2
D
ES
IG
A7
B0
B1
GLB
Logic
Array
D Q
D Q
Global Routing Pool
(GRP)
B5
D Q
A3
A4
A5
A6
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0919/2096
f
max
= 125 MHz Maximum Operating Frequency
t
pd
= 7.5 ns Propagation Delay
TTL Compatible Inputs and Outputs
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine
Glue Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
09
6E
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
The ispLSI 2096 and 2096A are High Density Program-
mable Logic Devices. The devices contain 96 Registers,
96 Universal I/O pins, six Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2096 and 2096A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2096 and 2096A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…C7
(Figure 1). There are a total of 24 GLBs in the ispLSI 2096
and 2096A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
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Description
August 2006
2096_09
1
Specifications
ispLSI 2096/A
Functional Block Diagram
Figure 1. ispLSI 2096/A Functional Block Diagram
GOE 0
GOE 1
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
N
B7
Megablock
Generic Logic
Blocks (GLBs)
C7
Output Routing Pool (ORP)
Output Routing Pool (ORP)
S
Select devices have been discontinued.
See Ordering Information section for product status.
C0
Input Bus
Input Bus
Output Routing Pool (ORP)
Input Bus
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
EW
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
A1
A2
Global
Routing
Pool
(GRP)
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
D
ES
IG
B6
B5
B4
C6
C5
C4
C3
C2
C1
IN 5
IN 4
A0
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
A3
A4
A5
A6
A7
R
B0
N
B1
B2
B3
Output Routing Pool (ORP)
Input Bus
FO
SDO
RESET
ispEN
Output Routing Pool (ORP)
Input Bus
CLK 0
CLK 1
CLK 2
I/O 44
I/O 45
I/O 46
I/O 47
6E
I/O 28
I/O 29
I/O 30
I/O 31
IN 2
SCLK/IN 3
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
0917
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
I2
09
is
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The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2096 and 2096A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096 and 2096A device contains three Megablocks.
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Y0
Y1
Y2
Specifications
ispLSI 2096/A
Absolute Maximum Ratings
1
Supply Voltage V
cc
...................................-0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
N
EW
D
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IG
MIN.
4.75
4.5
0
2.0
UNITS
pf
pf
S
Select devices have been discontinued.
See Ordering Information section for product status.
MAX.
5.25
5.5
0.8
V
cc
+1
UNITS
V
V
V
V
Table 2 - 0005/2096
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
V
cc
V
IL
V
IH
T
A
= -40°C to + 85°C
I2
C
1
C
2
I/O and Dedicated Input Capacitance
Clock Capacitance
09
SYMBOL
PARAMETER
6E
Capacitance (T
A
=25°C, f=1.0 MHz)
FO
TYPICAL
8
15
R
N
T
A
= 0°C to + 70°C
TEST CONDITIONS
V
CC
= 5.0V, V
I/O, IN
= 2.0V
V
CC
= 5.0V, V
Y
= 2.0V
Table 2-0006a
Data Retention Specifications
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PARAMETER
LS
MINIMUM
20
10000
MAXIMUM
–
–
UNITS
Years
Cycles
Table 2-0008A-isp
Data Retention
Erase/Reprogram Cycles
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Specifications
ispLSI 2096/A
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
-125
Others
1.5V
1.5V
See Figure 2
Table 2-0003/2096
Figure 2. Test Load
+ 5V
R1
≤
2 ns
≤
3 ns
N
D
ES
IG
R2
MIN.
–
2.4
–
–
–
–
–
Commercial
Industrial
–
–
TYP.
–
–
–
–
–
–
–
150
150
3
Device
Output
S
CL
*
Test
Point
Select devices have been discontinued.
See Ordering Information section for product status.
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
470Ω
∞
470Ω
∞
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
*
CL includes Test Fixture and Probe Capacitance.
0213/2096
C
Table 2-0004/2096
DC Electrical Characteristics
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
6E
Over Recommended Operating Conditions
CONDITION
MAX. UNITS
0.4
–
-10
10
-150
-150
-200
295
–
V
V
μA
μA
μA
μA
mA
mA
mA
Output Short Circuit Current
Operating Power Supply Current
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V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2, 4
09
I
OL
= 8 mA
I
OH
= -4 mA
0V
≤
V
IN
≤
V
IL
(Max.)
3.5V
≤
V
IN
≤
V
CC
0V
≤
V
IN
≤
V
IL
(Max.)
0V
≤
V
IN
≤
V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 3.0V
f
CLOCK
= 1 MHz
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
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1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25°C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I
CC
.
Table 2-0007/2096
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Specifications
ispLSI 2096/A
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
2
#
COND.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
1
2
3
4
5
6
7
8
9
4
1
DESCRIPTION
-125
–
–
3
1
tsu2 + tco1
-100
–
–
100
77.0
100
6.5
–
10.0
13.0
–
–
–
–
–
–
-80
15.0
18.5
MIN. MAX. MIN. MAX. MIN. MAX.
7.5
10.0
–
–
–
–
–
–
–
10.0
–
12.0
12.0
7.0
7.0
–
–
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
1.
2.
3.
4.
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
Clock Frequency with External Feedback
(
125
81.0
57.0
83.0
9.0
–
0.0
–
–
10.0
–
–
–
–
6.0
6.0
100
125
5.0
–
0.0
6.0
–
0.0
–
–
–
–
–
4.0
4.0
5.0
N
11.0
0.0
)
S
–
–
–
–
6.5
–
–
8.0
–
17.0
–
18.0
18.0
12.0
12.0
–
–
Select devices have been discontinued.
See Ordering Information section for product status.
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Product Term OE, Enable
15 Product Term OE, Disable
16 Global OE, Enable
17 Global OE, Disable
EW
N
R
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
FO
D
ES
IG
4.0
5.0
–
–
–
13.5
–
15.0
15.0
9.0
9.0
–
–
0.0
–
–
6.5
–
–
–
–
5.0
5.0
8.0
0.0
4.5
6.0
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09
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
6E
Table 2-0030/2096
5
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