Am29LV116D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
21359
Revision
E
Amendment
2
Issue Date
May 27, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29LV116D
16 Megabit (2 M x 8-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
Single power supply operation
— 2.7 to 3.6 volt read and write operations for
battery-powered applications
■
Manufactured on 0.23 µm process technology
— Compatible with and replaces Am29LV116B
device
■
High performance
— Access times as fast as 70 ns
■
Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 15 mA program/erase current
■
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
■
Top or bottom boot block configurations
available
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Minimum 1,000,000 write cycle guarantee
per sector
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
Package option
— 40-pin TSOP
■
CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■
Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
Publication#
21359
Rev:
E
Amendment/+2
Issue Date:
May 27, 2004
GENERAL DESCRIPTION
The Am29LV116D is a 16 Mbit, 3.0 Volt-only Flash
memory organized as 2,097,152 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)
data appears on DQ7–DQ0. All read, program, and
erase operations are accomplished using only a single
power supply. The device can also be programmed in
standard EPROM programmers.
The standard device offers access times of 70, 90, and
120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron injec-
tion.
4
Am29LV116D
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Standard Products .................................................................... 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29LV116D Device Bus Operations ..............................10
DQ3: Sector Erase Timer ....................................................... 26
Figure 6. Toggle Bit Algorithm........................................................ 26
Table 10. Write Operation Status ................................................... 27
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 28
Figure 7. Maximum Negative Overshoot Waveform ...................... 28
Figure 8. Maximum Positive Overshoot Waveform........................ 28
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Am29LV116DT Top Boot Sector Address Table ..............12
Table 3. Am29LV116DB Bottom Boot Sector Address Table .........13
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
CMOS Compatible .................................................................. 29
Zero Power Flash ................................................................... 30
Figure 9. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 30
Figure 10. Typical I
CC1
vs. Frequency ........................................... 30
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. Test Setup..................................................................... 31
Table 11. Test Specifications ......................................................... 31
Key to Switching Waveforms .................................................. 31
Figure 12. Input Waveforms and Measurement Levels ................. 31
Autoselect Mode ..................................................................... 14
Table 4. Am29LV116D Autoselect Codes (High Voltage Method) ..14
Sector Protection/Unprotection ............................................... 14
Temporary Sector Unprotect .................................................. 14
Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 15
Figure 2. Temporary Sector Unprotect Operation........................... 16
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
Read Operations .................................................................... 32
Figure 13. Read Operations Timings ............................................. 32
Hardware Reset (RESET#) .................................................... 33
Figure 14. RESET# Timings .......................................................... 33
Hardware Data Protection ...................................................... 16
Low V
CC
Write Inhibit .............................................................. 16
Write Pulse “Glitch” Protection ............................................... 16
Logical Inhibit .......................................................................... 16
Power-Up Write Inhibit ............................................................ 16
Common Flash Memory Interface (CFI) . . . . . . . 16
Table 5. CFI Query Identification String ..........................................17
Table 6. System Interface String .....................................................17
Table 7. Device Geometry Definition ..............................................18
Table 8. Primary Vendor-Specific Extended Query ........................18
Erase/Program Operations ..................................................... 34
Figure 15. Program Operation Timings..........................................
Figure 16. Chip/Sector Erase Operation Timings ..........................
Figure 17. Data# Polling Timings (During Embedded Algorithms).
Figure 18. Toggle Bit Timings (During Embedded Algorithms)......
Figure 19. DQ2 vs. DQ6.................................................................
35
35
36
36
37
Temporary Sector Unprotect .................................................. 37
Figure 20. Temporary Sector Unprotect Timing Diagram .............. 37
Figure 21. Sector Protect/Unprotect Timing Diagram .................... 38
Figure 22. Alternate CE# Controlled Write Operation Timings ...... 40
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 19
Reading Array Data ................................................................ 19
Reset Command ..................................................................... 19
Autoselect Command Sequence ............................................ 19
Byte Program Command Sequence ....................................... 19
Unlock Bypass Command Sequence ..................................... 20
Figure 3. Program Operation .......................................................... 20
Chip Erase Command Sequence ........................................... 20
Sector Erase Command Sequence ........................................ 21
Erase Suspend/Erase Resume Commands ........................... 21
Figure 4. Erase Operation............................................................... 22
Command Definitions ............................................................. 23
Table 9. Am29LV116D Command Definitions ...............................23
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 24
DQ7: Data# Polling ................................................................. 24
Figure 5. Data# Polling Algorithm ................................................... 24
RY/BY#: Ready/Busy# ........................................................... 25
DQ6: Toggle Bit I .................................................................... 25
DQ2: Toggle Bit II ................................................................... 25
Reading Toggle Bits DQ6/DQ2 .............................................. 25
DQ5: Exceeded Timing Limits ................................................ 26
Erase and Programming Performance . . . . . . . 41
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 41
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 41
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 42
TS 040—40-Pin Standard TSOP ............................................ 42
TSR040—40-Pin Reverse TSOP ........................................... 43
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44
Revision A (October 1997) ..................................................... 44
Revision B (October 1997) ..................................................... 44
Revision C (December 1997) ................................................. 44
Revision C+1 (January 1998) ................................................. 44
Revision C+2 (March 1998) .................................................... 44
Revision C+3 (August 1998) ................................................... 44
Revision D (January 1999) ..................................................... 44
Revision E (February 2, 2000) ................................................ 44
Revision E+1 (November 7, 2000) ......................................... 44
Added table of contents. Deleted burn-in option in ordering infor-
mation section. ....................................................................... 44
Revision E+2 (May 27, 2004) ................................................. 44
Am29LV116D
5
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