IC41C16105
IC41LV16105
.EATURES
1M x 16 (16-MBIT) DYNAMIC RAM
WITH .AST PAGE MODE
TTL compatible inputs and outputs; tristate I/O
Refresh Interval: 1,024 cycles/16 ms
Refresh Mode:
RAS-Only, CAS-before-RAS
(CBR),
Hidden
JEDEC standard pinout
Single power supply:
5V ± 10% (IC41C16105)
3.3V ± 10% (IC41LV16105)
Byte Write and Byte Read operation via two
CAS
Industrail temperature range -40
o
C to 85
o
C
DESCRIPTION
The
1+51
IC41C16105 and IC41LV16105 are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access
Memories. .ast Page Mode allows 1,024 random accesses
within a single row with access cycle time as short as 20 ns per
16-bit word. The Byte Write control, of upper and lower byte,
makes the IC41C16105 ideal for use in 16-, 32-bit wide data
bus systems.
These features make the IC41C16105 and IC41LV16105
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IC41C16105 and IC41LV16105 are packaged in a
42-pin 400mil SOJ and 400mil 44- (50-) pin TSOP-2.
KEY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. .ast Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-50
50
13
25
20
84
-60
60
15
30
25
104
Unit
ns
ns
ns
ns
ns
PIN CON.IGURATIONS
44(50)-Pin TSOP-2
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
42-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
S2-1
IC41C16105
IC41LV16105
.unctional Description
The IC41C16105 and IC41LV16105 is a CMOS DRAM
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 10 address bits. These
are entered ten bits (A0-A9) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS
is used to latch the first ten bits and
CAS
is used the
latter ten bits.
The IC41C16105 and IS41LV16105 has two
CAS
controls,
LCAS
and
UCAS.
The
LCAS
and
UCAS
inputs internally
generates a
CAS
signal functioning in an identical manner
to the single
CAS
input on the other 1M x 16 DRAMs. The
key difference is that each
CAS
controls its corresponding
I/O tristate logic (in conjunction with
OE
and
WE
and
RAS).
LCAS
controls I/O0 through I/O7 and
UCAS
controls I/O8
through I/O15.
The IC41C16105 and IC41LV16105
CAS
function is de-
termined by the first
CAS
(LCAS or
UCAS)
transitioning
LOW and the last transitioning back HIGH. The two
CAS
controls give the IC41C16105 and IC41LV16105 both
BYTE READ and BYTE WRITE cycle capabilities.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE,
whichever occurs
last.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0
through A9) with
RAS
at least once every 16 ms. Any
read, write, read-modify-write or
RAS-only
cycle re-
freshes the addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while holding
CAS
LOW. In
CAS-before-RAS
refresh
cycle, an internal 10-bit counter provides the row
addresses and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
S2-4
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
IC41C16105
IC41LV16105
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
CC
I
OUT
P
D
T
A
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Commercial Operation Temperature
Industrail Operation Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
1.0 to +7.0
0.5 to +4.6
1.0 to +7.0
0.5 to +4.6
50
1
0 to +70
40 to +85
55 to +125
Unit
V
V
mA
W
°C
°C
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
V
CC
V
IH
V
IL
T
A
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Commercial Ambient Temperature
Industrail Ambient Temperature
5V
3.3V
5V
3.3V
5V
3.3V
Min.
4.5
3.0
2.4
2.0
1.0
0.3
0
40
Typ.
5.0
3.3
Max.
5.5
3.6
V
CC
+ 1.0
V
CC
+ 0.3
0.8
0.8
70
85
Unit
V
V
V
°C
°C
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A9
Input Capacitance:
RAS, UCAS, LCAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O15
Max.
5
7
7
Unit
p.
p.
p.
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz,
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
S2-5
FPGA/CPLD
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