K7M403625A
K7M401825A
Document Title
128Kx36 & 256Kx18 Flow-Through NtRAM
TM
128Kx36 & 256Kx18-Bit Flow Through NtRAM
TM
Revision History
Rev. No.
0.0
0.1
History
1. Initial document.
1. Changed DC condition at Icc and I
SB.
Icc ; from 320mA to 370mA at -65,
from 300mA to 350mA at -75,
from 280mA to 330mA at -80,
from 260mA to 310mA at -90,
I
SB
; from 130mA
from 120mA
from 110mA
from 100mA
1.0
to
to
to
to
140mA
130mA
120mA
110mA
at
at
at
at
-65,
-75,
-80,
-90,
May. 15. 2000
Final
Draft Date
Jan. 20. 2000
April. 03. 2000
Remark
Preliminary
Preliminary
1. Final spec release
2. Changed input & output capacitance.
C
IN
; from 6pF to 5pF,
C
OUT
; from 8pF to 7pF,
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
May 2000
Rev 1.0
K7M403625A
K7M401825A
128Kx36 & 256Kx18 Flow-Through NtRAM
TM
128Kx36 & 256Kx18-Bit Flow-Through NtRAM
TM
FEATURES
• V
DD
=3.3V+0.165V/-0.165V Power Supply.
• V
DDQ
Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A Package.
GENERAL DESCRIPTION
The K7M403625A and K7M401825A are 4,718,592-bit Syn-
chronous Static SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory uti-
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incomming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
The K7M403625A and K7M401825A are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP packages. Multiple power and ground pins
minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -65 -75 -80 -90 Unit
t
CYC
t
CD
t
OE
7.5
6.5
3.5
8.5
7.5
3.5
10
8.0
3.5
12
9.0
3.5
ns
ns
ns
LOGIC BLOCK DIAGRAM
LBO
A [0:16]or
A [0:17]
ADDRESS
REGISTER
A
2
~A
16
or A
2
~A
17
A
0
~A
1
BURST
ADDRESS
COUNTER
A′
0
~A′
1
128Kx36 , 256Kx18
MEMORY
ARRAY
CLK
CKE
K
WRITE
ADDRESS
REGISTER
K
DATA-IN
REGISTER
CONTROL
LOGIC
CS
1
CS
2
CS
2
ADV
WE
BW
x
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa
0
~ DQb
8
DQPa ~ DQPd
CONTROL
REGISTER
CONTROL
LOGIC
BUFFER
36 or 18
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung,
-2-
May 2000
Rev 1.0
K7M403625A
K7M401825A
PIN CONFIGURATION
(TOP VIEW)
BWd
128Kx36 & 256Kx18 Flow-Through NtRAM
TM
BWb
BWa
BWc
CKE
ADV
N.C.
N.C.
83
CLK
CS
1
CS
2
CS
2
V
DD
V
SS
WE
OE
A
6
A
7
A
8
82
100
99
98
97
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
11
A
12
A
13
A
14
A
15
PIN NAME
SYMBOL
A
0
- A
16
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37
44,45,46,47,48,49
50,81,82,99,100
85
88
89
87
98
97
92
93,94,95,96
86
64
31
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
V
DDQ
V
SSQ
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
TQFP PIN NO.
15,16,41,65,91
14,17,40,66,67,90
38,39,42,43,83,84
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx(x=a,b,c,d)
OE
ZZ
LBO
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
LBO
V
SS
Output Power Supply
(2.5V or 3.3V)
Output Ground
Notes :
1. The pin 83 is reserved for address bit for the 8Mb NtRAM.
2. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-3-
A
16
50
DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
Vss
V
DD
V
DD
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7M403625A(128Kx36)
DQPb
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
V
SS
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa
96
May 2000
Rev 1.0
K7M403625A
K7M401825A
PIN CONFIGURATION
(TOP VIEW)
128Kx36 & 256Kx18 Flow-Through NtRAM
TM
BWb
BWa
CKE
ADV
CS
2
N.C.
N.C.
N.C.
N.C.
83
CLK
CS
1
CS
2
V
DD
V
SS
WE
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
11
A
12
A
13
A
14
A
15
A
16
PIN NAME
SYMBOL
A
0
- A
17
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,44
45,46,47,48,49,50,80
81,82,99,100
85
88
89
87
98
97
92
93,94
86
64
31
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
TQFP PIN NO.
15,16,41,65,91
14,17,40,66,67,90
1,2,3,6,7,25,28,29,30,38,39,
42,43,51,52,53,56,57,75,78,
79,83,84,95,96
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx(x=a,b)
OE
ZZ
LBO
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
LBO
V
SS
DQa
0
~a
8
DQb
0
~b
8
Data Inputs/Outputs
V
DDQ
V
SSQ
Output Power Supply
(2.5V or 3.3V)
Output Ground
A
17
50
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
8
DQb
7
V
SSQ
V
DDQ
DQb
6
DQb
5
V
SS
V
DD
V
DD
V
SS
DQb
4
DQb
3
V
DDQ
V
SSQ
DQb
2
DQb
1
DQb
0
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7M401825A(256Kx18)
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQa
0
DQa
1
DQa
2
V
SSQ
V
DDQ
DQa
3
DQa
4
V
SS
V
SS
V
DD
ZZ
DQa
5
DQa
6
V
DDQ
V
SSQ
DQa
7
DQa
8
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
Notes :
1. The pin 83 is reserved for address bit for the 8Mb NtRAM.
2. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-4-
May 2000
Rev 1.0
K7M403625A
K7M401825A
FUNCTION DESCRIPTION
128Kx36 & 256Kx18 Flow-Through NtRAM
TM
The K7M403625A and K7M401825A are NtRAM
TM
designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAM
TM
latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS
1
, CS
2
, CS
2
)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS
1
, CS
2
, CS
2
) are active, the write enable input signals WE are driven
high, and ADV driven low. Data appears at the outputs within the same clock cycle as the address for the data. Also during read oper-
ation OE must be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The Flow
Through NtRAM
TM
uses a late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required one cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Case 1
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
0
1
1
Case 2
A
0
1
0
1
0
A
1
1
1
0
0
Case 3
(Interleaved Burst, LBO=High)
Case 4
A
0
0
1
0
1
A
1
1
1
0
0
A
0
1
0
1
0
Fourth Address
Notes
: 1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
BQ TABLE
LBO PIN
LOW
First Address
Case 1
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
1
1
0
Case 2
A
0
1
0
1
0
A
1
1
1
0
0
Case 3
(Linear Burst, LBO=Low)
Case 4
A
0
0
1
0
1
A
1
1
0
0
1
A
0
1
0
1
0
Fourth Address
Notes
: 1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
-5-
May 2000
Rev 1.0
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