PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS85314I-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
F
EATURES
•
5 differential 2.5V/3.3V LVPECL outputs
•
Selectable differential CLK0, nCLK0 or LVCMOS inputs
•
CLK0, nCLK0 pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
CLK1 can accept the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 650MHz
•
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 400ps (maximum)
•
Propagation delay: CLK0, nCLK0, 2.1ns (maximum)
CLK1, 2.1ns (maximum)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
•
-40°C to 85°C ambient operating temperature
•
Compatible to part number MC100LVEL14
G
ENERAL
D
ESCRIPTION
The ICS85314I-01 is a low skew, high performance
1-to-5 Differential-to-3.3V LVPECL fanout buffer
HiPerClockS™
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.
The ICS85314I-01 has two selectable clock inputs.
The CLK0, nCLK0 pair can accept most standard differential
input levels. The single-ended CLK1 can accept LVCMOS or
LVTTL input levels. The clock enable is internally synchronized
to eliminate runt clock pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
,&6
Guaranteed output and part-to-part skew characteristics make
the ICS85314I-01 ideal for those applications demanding well
defined performance and repeatability.
B
LOCK
D
IAGRAM
nCLK_EN
D
Q
LE
CLK0
nCLK0
CLK1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
nCLK_EN
V
CC
nc
CLK1
CLK0
nCLK0
nc
CLK_SEL
V
EE
0
0
1
1
Q0
nQ0
Q1
nQ1
CLK_SEL
Q2
nQ2
Q3
nQ3
Q4
nQ4
ICS85314I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
ICS85314I-01
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
85314AGI-01
www.icst.com/products/hiperclocks.html
1
REV. B JULY 30, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS85314I-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
Type
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Clock select input. When HIGH, selects SCLK input.
Pulldown When LOW, selects CLK, nCLK inputs.
LVTTL / LVCMOS interface levels.
No connect.
Pullup
Inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
Pulldown Clock input. LVTTL / LVCMOS interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 6
7, 8
9 , 10
11
12
13, 17
14
15
16
18, 20
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
V
EE
CLK_SEL
nc
nCLK0
CLK0
CLK1
V
CC
Output
Output
Output
Output
Output
Power
Input
Unused
Input
Input
Input
Power
Positive supply pins.
Synchronizing clock enable. When LOW, clock outputs follow clock
19
nCLK_EN
Input
Pulldown input. When HIGH, Q outputs are forced low, nQ outputs are forced
high. LVTTL / LVCMOS interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
KΩ
KΩ
85314AGI-01
www.icst.com/products/hiperclocks.html
2
REV. B JULY 30, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS85314I-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
Inputs
Outputs
Selected Source
CLK0, nCLK0
CLK1
CLK0, nCLK0
Q0:Q4
Enabled
Enabled
Disabled; LOW
nQ0:nQ4
Enabled
Enabled
Disabled; HIGH
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
nCLK_EN
0
0
1
CLK_SEL
0
1
0
1
1
CLK1
Disabled; LOW
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1 inputs as described
in Table 3B.
Disabled
nCLK0
CLK0, CLK1
Enabled
nCLK_EN
nQ0:nQ4
Q0:Q4
F
IGURE
1 - nCLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK0 or CLK1
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK0
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q4
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ4
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
85314AGI-01
www.icst.com/products/hiperclocks.html
3
REV. B JULY 30, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS85314I-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
4.6V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CC
+ 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CCx
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
55
Maximum
3.8
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
nCLK_EN, CLK_SEL
CLK1
nCLK_EN, CLK_SEL
CLK1
CLK1,
CLK_SEL, nCLK_EN
CLK1,
CLK_SEL, nCLK_EN
Test Conditions
Minimum
2
2
-0.3
-0.3
V
IN
= V
CC
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
-5
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
1.3
150
Units
V
V
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK0
CLK0
nCLK0
CLK0
Test Conditions
V
CC
= V
IN
= 3.8V
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
V
CC
= 3.8V, V
IN
= 0V
-150
-5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
0.5
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
85314AGI-01
www.icst.com/products/hiperclocks.html
4
REV. B JULY 30, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS85314I-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 1.0
V
CC
- 1.7
1.0
Units
V
V
V
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
Output Frequency
Propagation Delay,
Low to High
CLK0, nCLK0;
NOTE 1
CLK1; NOTE 2
IJ 650MHz
IJ 250MHz
1.0
1.0
Test Conditions
Minimum
Typical
Maximum
650
2.1
2.1
50
400
20% to 80% @ 50MHz
20% to 80% @ 50MHz
CLK0, nCLK0
IJ 650MHz
200
200
45
700
700
55
55
Units
MHz
ns
ns
ps
ps
ps
ps
%
%
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Skew; NOTE 3, 5
Par t-to-Par t Skew; NOTE 4, 5
Output Rise Time
Output Fall Time
Output Duty Cycle
CLK1
IJ 250MHz
45
All parameters measured at 250MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Measured from V
CC
/2 input crossing point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
85314AGI-01
www.icst.com/products/hiperclocks.html
5
REV. B JULY 30, 2002
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