BX80528JK140GR datasheet, PDF - EEWORLD Datasheet

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BX80528JK140GR: DescriptionMicroprocessor, 32-Bit, 1400MHz, CMOS, PGA-423; CategoryThe embedded processor and controller Microcontrollers and processors; File Size762KB，90 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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BX80528JK140GR Overview

Microprocessor, 32-Bit, 1400MHz, CMOS, PGA-423

BX80528JK140GR Parametric

Parameter Name	Attribute value
Maker	Intel
Parts packaging code	PGA
package instruction	IPGA,
Contacts	423
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-XPGA-P423
length	53.34 mm
low power mode	YES
Number of terminals	423
Package body material	UNSPECIFIED
encapsulated code	IPGA
Package shape	SQUARE
Package form	GRID ARRAY, INTERSTITIAL PITCH
Certification status	Not Qualified
Maximum seat height	5.5118 mm
speed	1400 MHz
Maximum supply voltage	1.7 V
Minimum supply voltage	1.56 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	53.34 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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Intel

Pentium

4 Processor in the 423-pin

Package at 1.30, 1.40, 1.50, 1.60, 1.70, 1.80,

1.90 and 2 GHz

Datasheet

Product Features

Available

at 1.30, 1.40,1.50, 1.60, 1.70,

1.80, 1.90 and 2 GHz

Binary compatible with applications

running on previous members of the Intel

microprocessor line

Intel NetBurst™ micro-architecture

System bus frequency at 400 MHz

Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor

core frequency

Hyper Pipelined Technology

Advance Dynamic Execution

— Very deep out-of-order execution

— Enhanced branch prediction

Level 1 Execution Trace Cache stores 12K

micro-ops and removes decoder latency

from main execution loops

KB Level 1 data cache

256 KB Advanced Transfer Cache (on-die,

full speed Level 2 (L2) cache) with 8-way

associativity and Error Correcting Code

(ECC)

144 new Streaming SIMD Extensions 2

(SSE2) instructions

Enhanced floating point and multimedia

unit for enhanced video, audio, encryption,

and 3D performance

Power Management capabilities

— System Management mode

— Multiple low-power states

Optimized for 32-bit applications running

on advanced 32-bit operating systems

8-way cache associativity provides

improved cache hit rate on reads/store

operations.

The Intel

Pentium

processor is designed for high-performance desktops and entry level

workstations. It is binary compatible with previous Intel Architecture processors. The Pentium 4

processor provides great performance for applications running on advanced operating systems

such as Windows* 98, Windows ME, Windows 2000 and UNIX*. This is achieved by the Intel

NetBurst™ micro-architecture which brings a new level of performance for system buyers. The

Pentium

processor extends the power of the Pentium

III

processor with performance headroom

for advanced audio and video internet capabilities. Systems based on Pentium

processors also

include the latest features to simplify system management and lower the total cost of ownership

for large and small business environments. The Pentium

processor offers great performance

for today’s and tomorrow’s applications.

Order Number: 249198-005

August 2001

Contents

1.0

Introduction

.................................................................................................................. 7

1.1

1.2

Terminology........................................................................................................... 8

1.1.1 Processor Packaging Terminology........................................................... 8

References ............................................................................................................ 9

System Bus and GTLREF ...................................................................................11

Power and Ground Pins ......................................................................................11

Decoupling Guidelines ........................................................................................11

2.3.1 VCC Decoupling .....................................................................................12

2.3.2 System Bus AGTL+ Decoupling.............................................................12

2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking .......................12

Voltage Identification ...........................................................................................12

2.4.1 Phase Lock Loop (PLL) Power and Filter...............................................13

Reserved, Unused Pins, and TESTHI[10:0]........................................................15

System Bus Signal Groups .................................................................................16

Asynchronous GTL+ Signals...............................................................................17

Test Access Port (TAP) Connection....................................................................17

Maximum Ratings................................................................................................18

Processor DC Specifications...............................................................................18

AGTL+ System Bus Specifications .....................................................................21

System Bus AC Specifications ............................................................................22

Processor AC Timing Waveforms .......................................................................25

BCLK Signal Quality Specifications and Measurement Guidelines.....................31

System Bus Signal Quality Specifications and Measurement Guidelines...........32

System Bus Signal Quality Specifications and Measurement Guidelines...........33

3.3.1 Overshoot/Undershoot Guidelines .........................................................33

3.3.2 Overshoot/Undershoot Magnitude .........................................................34

3.3.3 Overshoot/Undershoot Pulse Duration...................................................34

3.3.4 Activity Factor .........................................................................................34

3.3.5 Reading Overshoot/Undershoot Specification Tables............................35

3.3.6 Determining if a System Meets the Over/Undershoot Specifications .....35

Package Load Specifications ..............................................................................46

Processor Insertion Specifications ......................................................................47

Processor Mass Specifications ...........................................................................47

Processor Materials.............................................................................................47

Processor Markings.............................................................................................48

Processor Pin-Out Coordinates...........................................................................48

Processor Pin Assignments ................................................................................51

5.1.1 Pin Listing by Pin Name .........................................................................51

5.1.2 Pin Listing by Pin Number ......................................................................57

2.0

Electrical Specifications

........................................................................................11

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

3.0

System Bus Signal Quality Specifications

....................................................31

3.1

3.2

3.3

4.0

Package Mechanical Specifications

.........................................................................43

4.1

4.2

4.3

4.4

4.5

4.6

5.0

Pin Listing and Signal Definitions

...........................................................................51

5.1

Contents

5.2

Alphabetical Signals Reference .......................................................................... 63

Thermal Specifications........................................................................................ 72

Thermal Analysis................................................................................................. 72

6.2.1 Measurements For Thermal Specifications............................................ 72

6.2.1.1 Processor Case Temperature Measurement ............................ 72

Power-On Configuration Options ........................................................................ 75

Clock Control and Low Power States.................................................................. 75

7.2.1 Normal State—State 1 ........................................................................... 75

7.2.2 AutoHALT Powerdown State—State 2 .................................................. 75

7.2.3 Stop-Grant State—State 3 ..................................................................... 76

7.2.4 HALT/Grant Snoop State—State 4 ........................................................ 77

7.2.5 Sleep State—State 5.............................................................................. 77

7.2.6 Deep Sleep State—State 6 .................................................................... 78

Thermal Monitor .................................................................................................. 78

7.3.1 Thermal Diode........................................................................................ 79

Introduction ......................................................................................................... 81

Mechanical Specifications................................................................................... 81

8.2.1 Boxed Processor Fan Heatsink Dimensions .......................................... 82

8.2.2 Boxed Processor Fan Heatsink Weight.................................................. 83

8.2.3 Boxed Processor Retention Mechanism and Fan Heatsink Supports.... 83

Boxed Processor Requirements ......................................................................... 84

8.3.1 Fan Heatsink Power Supply ................................................................... 84

Thermal Specifications........................................................................................ 85

8.4.1 Boxed Processor Cooling Requirements ............................................... 85

8.4.2 Variable Speed Fan ............................................................................... 87

Logic Analyzer Interface (LAI)............................................................................ 89

9.1.1 Mechanical Considerations .................................................................... 89

9.1.2 Electrical Considerations........................................................................ 89

6.0

Thermal Specifications and Design Considerations

................................. 71

6.1

6.2

7.0

Features

....................................................................................................................... 75

7.1

7.2

7.3

8.0

Boxed Processor Specifications

................................................................................ 81

8.1

8.2

8.3

8.4

9.0

Debug Tools Specifications

........................................................................................ 89

9.1

Contents

Figures

Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................14

Phase Lock Loop (PLL) Filter Requirements ......................................................15

AC Test Circuit ....................................................................................................26

TCK Clock Waveform..........................................................................................26

Differential Clock Waveform................................................................................27

System Bus Common Clock Valid Delay Timings...............................................27

System Bus Reset and Configuration Timings....................................................28

Source Synchronous 2X (Address) Timings .......................................................28

Source Synchronous 4X Timings ........................................................................29

Power-On Reset and Configuration Timings.......................................................29

Test Reset Timings .............................................................................................30

BCLK[1:0] Signal Integrity Waveform..................................................................32

Low-to-High System Bus Receiver Ringback Tolerance.....................................33

High-to-Low System Bus Receiver Ringback Tolerance.....................................33

Maximum Acceptable Overshoot/Undershoot Waveform ...................................41

Exploded View of Processor Components on a System Board ..........................43

Processor Package .............................................................................................44

Processor Cross-Section and Keep-in ................................................................45

Processor Pin Detail............................................................................................46

IHS Flatness Specification ..................................................................................46

Processor Markings.............................................................................................48

Processor Pinout Diagram - Bottom View ...........................................................49

Example Thermal Solution (Not to scale)............................................................71

Guideline Locations for Case Temperature (TCASE) Thermocouple Placement73

Technique for Measuring with 0 Degree Angle Attachment ................................73

Technique for Measuring with 90 Degree Angle Attachment ..............................73

Stop Clock State Machine ...................................................................................76

Mechanical Representation of the Boxed Pentium 4 Processor .........................81

Side View Space Requirements for the Boxed Processor ..................................82

Top View Space Requirements for the Boxed Processor ...................................83

Boxed Processor Fan Heatsink Power Cable Connector Description.................84

Acceptable System Board Power Header Placement

Relative to Processor Socket ..............................................................................85

Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view).86

Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view).86

Boxed Processor Fan Heatsink Set Points .........................................................87

BX80528JK140GR Related Products

	BX80528JK140GR	BX80528JK130GR	BX80528JK150GR	BX80528JK170G
Description	Microprocessor, 32-Bit, 1400MHz, CMOS, PGA-423	Microprocessor, 32-Bit, 1300MHz, CMOS, PGA-423	Microprocessor, 32-Bit, 1500MHz, CMOS, PGA-423	Microprocessor, 32-Bit, 1700MHz, CMOS, PGA-423
Maker	Intel	Intel	Intel	Intel
Parts packaging code	PGA	PGA	PGA	PGA
package instruction	IPGA,	IPGA,	IPGA,	IPGA,
Contacts	423	423	423	423
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
Address bus width	36	36	36	36
bit size	32	32	32	32
boundary scan	YES	YES	YES	YES
maximum clock frequency	100 MHz	100 MHz	100 MHz	100 MHz
External data bus width	64	64	64	64
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES	YES
JESD-30 code	S-XPGA-P423	S-XPGA-P423	S-XPGA-P423	S-XPGA-P423
length	53.34 mm	53.34 mm	53.34 mm	53.34 mm
low power mode	YES	YES	YES	YES
Number of terminals	423	423	423	423
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	IPGA	IPGA	IPGA	IPGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.5118 mm	5.5118 mm	5.5118 mm	5.5118 mm
speed	1400 MHz	1300 MHz	1500 MHz	1700 MHz
Maximum supply voltage	1.7 V	1.7 V	1.7 V	1.75 V
Minimum supply voltage	1.56 V	1.565 V	1.555 V	1.58 V
surface mount	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
width	53.34 mm	53.34 mm	53.34 mm	53.34 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR
Base Number Matches	1	1	1	-

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