K4D551638D-TC
256M GDDR SDRAM
256Mbit GDDR SDRAM
4M x 16Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
Revision 1.8
October 2003
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev 1.8 (Oct. 2003)
K4D551638D-TC
Revision History
Revision 1.8 (October 6, 2003)
• Added Lead free package part number in the data sheet.
256M GDDR SDRAM
Revision 1.7 (August 5, 2003)
• Added K4D551638D-TC45 in the spec
Revision 1.6 (July 21, 2003)
• Removed K4D551638D-TC30 from the spec
• Added K4D551638D-TC2A in the spec
Revision 1.5 (July 14, 2003)
• Added K4D551638D-TC30 in the spec
Revision 1.4 (June 16, 2003)
• Changed tRCDRD of K4D551638D-TC33/36 from 4tCK to 5tCK
• Changed tRCDWR of K4D551638D-TC33/36 from 2tCK to 3tCK
Revision 1.3 (April 11, 2003)
• Added K4D551638D-TC60 in the spec.
• Changed AC/DC parameters’ value of K4D551638D-TC50.
• Refresh cycle period of K4D551638D-TC50/60 is 8K/64ms.
Revision 1.1 (March 21, 2003)
• Changed VDD and VDDQ spec from 2.5V+5% to 2.6V+0.1V for all the frequency
Revision 1.0 (February 27, 2003)
• Changed the CAS Latency (CL) of K4D551638D-TC40 from 3 to 4
• Defined DC spec.
Revision 0.0 (January 16, 2003) -
Target Spec
• Defined Target Specification
- 2 -
Rev 1.8 (Oct. 2003)
K4D551638D-TC
256M GDDR SDRAM
4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 2.6V + 0.1V power supply for device operation
• 2.6V + 0.1V power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3, 4 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 2 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle) for -TC2A/33/36/40/45
• 64ms refresh period (8K cycle) for -TC50/60
• 66pin TSOP-II
• Maximum clock frequency up to 350MHz
• Maximum data rate up to 700Mbps/pin
ORDERING INFORMATION
Part NO.
K4D551638D-TC2A*
K4D551638D-TC33
K4D551638D-TC36
K4D551638D-TC40
K4D551638D-TC45
K4D551638D-TC50
K4D551638D-TC60*
Max Freq.
350MHz
300MHz
275MHz
250MHz
222MHz
200MHz
166MHz
Max Data Rate
700Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
444Mbps/pin
400Mbps/pin
333Mbps/pin
SSTL_2
66pin TSOP-II
Interface
Package
1. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V
2. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%.
3. K4D551638D-LC is the Lead free package part number
GENERAL DESCRIPTION
FOR 4M x 16Bit x 4 Bank DDR SDRAM
The K4D551638D is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by
16 bits, fabricated with SAMSUNG
’
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev 1.8 (Oct. 2003)
K4D551638D-TC
PIN CONFIGURATION
(Top View)
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
256M GDDR SDRAM
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm Pin Pitch)
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
CAS
WE
L(U)DQS
L(U)DM
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA
0
, BA
1
A
0
~A
12
DQ
0
~ DQ
15
V
DD
V
SS
V
DDQ
V
SSQ
NC
VREF
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ
’
s
Ground for DQ
’
s
No Connection
Reference voltage
- 4 -
Rev 1.8 (Oct. 2003)
K4D551638D-TC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK, CK*1
Input
Type
256M GDDR SDRAM
Function
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
’
s and DM
’
s that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS
corresponds to the data on DQ8-DQ15.
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on
DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
12
, Column addresses : CA
0
~ CA
8
.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommended to be left "No connection" on the device
CKE
Input
CS
Input
RAS
CAS
WE
Input
Input
Input
LDQS,UDQS
Input/Output
LDM,UDM
DQ
0
~ DQ
15
BA
0
, BA
1
A
0
~ A
12
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
NC/RFU
Input
Input/Output
Input
Input
Power Supply
Power Supply
Power Supply
No connection/
Reserved for future use
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
- 5 -
Rev 1.8 (Oct. 2003)
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