PPC405EX-NPB533TZ datasheet, PDF

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PPC405EX-NPB533TZ: DescriptionRISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA388, 27 X 27 MM, PLASTIC, MS-034C, EBGA-388; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，71 Pages; ManufacturerApplied Micro Circuits (MACOM)

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PPC405EX-NPB533TZ Overview

RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA388, 27 X 27 MM, PLASTIC, MS-034C, EBGA-388

PPC405EX-NPB533TZ Parametric

Parameter Name	Attribute value
Maker	Applied Micro Circuits (MACOM)
Parts packaging code	BGA
package instruction	BGA,
Contacts	388
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width
bit size	32
boundary scan	YES
maximum clock frequency	666.66 MHz
External data bus width
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B388
length	27 mm
low power mode	YES
Number of terminals	388
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	2.65 mm
speed	533 MHz
Maximum supply voltage	1.3 V
Minimum supply voltage	1.1 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	27 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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Part Number 405EX

Revision 1.12 - Novenber 20, 2007

405EX

Features

Preliminary Data Sheet

PowerPC 405EX Embedded Processor

• AMCC PowerPC



405 32-bit RISC processor core

operating from 333MHz to 600MHz including

16KB I- and D-caches with parity checking

• On-chip 128-bit processor local bus (PLB)

operating up to 200MHz

• On-chip 32-bit peripheral bus (OPB) operating up

to 100 MHz

• External 8-,16-, or 32-bit peripheral bus (EBC)

operating up to 100MHz

• External bus master (EBM) operating up to

100MHz

• On-chip Security feature with True Random

Number generation

• Eight- and 16-bit NAND Flash interface

• Inter-chip connectivity (SCP and IIC)

• Boot from NOR Flash on the external peripheral

bus or NAND Flash on the NAND Flash interface

• DMA (4-channel) support for all on-chip slaves

and external bus, UARTs, and devices on the EBC

• DDR1/2 SDRAM interface operating up to 400

Mbps

• Two one-lane PCI Express interfaces operating up

to 2.5 Gbps

• Two Gigabit Ethernet interfaces (half- and full-

duplex) to external PHY (GMII/RGMII)

• USB 2.0 OTG port configurable as either Host or

Device

• Programmable universal interrupt controller (UIC)

• General Purpose Timer (GPT)

• Up to two serial ports (16750 compatible UART)

• Two IIC interfaces operating up to 400kHz and

supporting all standard IIC EEPROMs

• One SCP (SPI) synchronous full-duplex channel

operating up to 25 MHz

• General purpose I/Os (GPIOs), each with

programmable interrupts and outputs

• Supports JTAG for board-level testing

• System power management, low power

dissipation and small form factor

• Available in a RoHS compliant (lead-free) package

Description

With speeds up to 600MHz, a flexible off-chip memory

architecture, and a diverse communications package

that includes PCI Express, USB 2.0 OTG, and

10/100/1000 Ethernet, the PowerPC 405EX

embedded processor provides a low power and small

footprint system-on-a-chip (SOC) solution for a wide

range of high performance, cost-constrained

embedded applications. This includes wireless LAN

applications, security appliances, internet appliances,

line cards, and intelligent USB peripherals. It is an

easily programmable general purpose, 32-bit RISC

controller that offers an upgrade path for applications

in need of performance and connectivity

improvements.

Technology: Cu-08 CMOS, 90nm

Package: 388-ball, 27mm

27mm, enhanced plastic

ball grid array (EPBGA), 1mm ball pitch

Power consumption (est.): less than 2W, typical

Voltages required: 3.3V, 2.5V, 1.8V (DDR2 SDRAM

only), and 1.2V

AMCC Proprietary

PPC405EX – PowerPC 405EX Embedded Processor

Revision 1.12 - Novenber 20, 2007

Preliminary Data Sheet

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power PC 405 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

USB 2.0 OTG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DDR1/2 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Security Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Serial Communication Port Interface (SCP/SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

General Purpose I/O (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Gigabit Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Signal Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Ratings and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

DDR 1/2 SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

PCI Express (PCI-E) I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

AMCC Proprietary

PPC405EX – PowerPC 405EX Embedded Processor

Revision 1.12 - Novenber 20, 2007

Preliminary Data Sheet

List of Tables

Table 1.

System Memory Address Map (4GB System Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2.

DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3.

Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4.

Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 5.

Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6.

Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 7.

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 8.

Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 9.

Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 10.

I/O Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 11.

Typical DC Power Supply Requirements with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 12.

Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 13.

DC Power Supply Loads with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 14.

DC Power Supply Loads with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 15.

System Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 16.

Peripheral Interface I/O Clock Timings (not SDRAM or PCI-E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 17.

I/O Specifications—All CPU Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 18.

I/O Specifications—333 MHz to 600 MHz CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 19.

DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 20.

DDR SDRAM Write Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 21.

I/O Timing—DDR SDRAM T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 22.

I/O Timing—DDR SDRAM T

and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 23.

I/O Timing—DDR SDRAM Write Timing T

and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 24.

I/O Timing—DDR SDRAM Read Timing T

and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 25.

PCI-E Receiver I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 26.

PCI-E Reference Clock I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 27.

PCI-E Transmitter I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 28.

Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

AMCC Proprietary

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