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IDT74FCT3807D

Description
Low Skew Clock Driver, FCT Series, 10 True Output(s), 0 Inverted Output(s), CMOS, CDIP20, CERDIP-20
Categorylogic    logic   
File Size47KB,6 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

IDT74FCT3807D Overview

Low Skew Clock Driver, FCT Series, 10 True Output(s), 0 Inverted Output(s), CMOS, CDIP20, CERDIP-20

IDT74FCT3807D Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeDIP
package instructionDIP,
Contacts20
Reach Compliance Codecompliant
Other featuresMAX PART TO PART SKEW = 1NS
seriesFCT
Input adjustmentSCHMITT TRIGGER
JESD-30 codeR-GDIP-T20
JESD-609 codee0
length25.34 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals20
Actual output times10
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)225
propagation delay (tpd)4.8 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.5 ns
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width7.62 mm
Base Number Matches1
IDT74FCT3807D/E
3.3V CMOS 1-TO-10 CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS
1-TO-10 CLOCK DRIVER
IDT74FCT3807D/E
FEATURES:
DESCRIPTION:
Advanced CMOS Technology
Guaranteed low skew < 100ps (max.)
Very low duty cycle distortion< 250ps (max.)
High speed propagation delay< 2ns (max.)
Very low CMOS power levels
TTL compatible inputs and outputs
1:10 fanout
Maximum output rise and fall time < 1ns (max.)
Low input capacitance: 3pF typical
V
CC
= 3.3V ± 0.3V
Inputs can be driven from 3.3V or 5V components
Operating frequency up to 166MHz
Available in SSOP and QSOP packages
The FCT3807 is a 3.3V clock driver built using advanced CMOS technol-
ogy. This low skew clock driver offers 1:10 fanout. The large fanout from a single
input reduces loading on the preceding driver and provides an efficient clock
distribution network. Multiple power and grounds reduce noise. Typical
applications are clock and signal distribution.
FUNCTIONAL BLOCK DIAGRAM
O
1
PIN CONFIGURATION
IN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
O
10
O
9
GND
O
8
V
CC
O
7
GND
O
6
O
5
O
2
GND
O
1
O
3
V
CC
O
2
O
4
GND
O
3
O
5
IN
O
6
V
CC
O
4
GND
O
7
SSOP/ QSOP
TOP VIEW
O
8
O
9
O
10
INDUSTRIAL TEMPERATURE RANGE
1
c
2001 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
JANUARY 2002
DSC-5865/13

IDT74FCT3807D Related Products

IDT74FCT3807D IDT74FCT3807E
Description Low Skew Clock Driver, FCT Series, 10 True Output(s), 0 Inverted Output(s), CMOS, CDIP20, CERDIP-20 Low Skew Clock Driver, FCT Series, 10 True Output(s), 0 Inverted Output(s), CMOS, CDFP20, CERPACK-20
Is it lead-free? Contains lead Contains lead
Is it Rohs certified? incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code DIP DFP
package instruction DIP, DFP,
Contacts 20 20
Reach Compliance Code compliant compliant
Other features MAX PART TO PART SKEW = 1NS MAX PART TO PART SKEW = 1NS
series FCT FCT
Input adjustment SCHMITT TRIGGER SCHMITT TRIGGER
JESD-30 code R-GDIP-T20 R-GDFP-F20
JESD-609 code e0 e0
Load capacitance (CL) 50 pF 50 pF
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Number of functions 1 1
Number of terminals 20 20
Actual output times 10 10
Maximum operating temperature 70 °C 70 °C
Package body material CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED
encapsulated code DIP DFP
Package shape RECTANGULAR RECTANGULAR
Package form IN-LINE FLATPACK
Peak Reflow Temperature (Celsius) 225 225
propagation delay (tpd) 4.8 ns 4.8 ns
Certification status Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.5 ns 0.5 ns
Maximum seat height 5.08 mm 2.3368 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3 V 3 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount NO YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE FLAT
Terminal pitch 2.54 mm 1.27 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 30
width 7.62 mm 6.92 mm
Base Number Matches 1 1
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