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IS62WV5128BLL-70T2

Description
Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, TSOP2-32
Categorystorage    storage   
File Size57KB,13 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
Download Datasheet Parametric View All

IS62WV5128BLL-70T2 Overview

Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, TSOP2-32

IS62WV5128BLL-70T2 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeTSOP2
package instructionTSOP2-32
Contacts32
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G32
JESD-609 codee0
length20.95 mm
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP32,.46
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply3/3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.000015 A
Minimum standby current1.2 V
Maximum slew rate0.035 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.5 V
Nominal supply voltage (Vsup)2.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width10.16 mm
Base Number Matches1
IS62WV5128ALL
IS62WV5128BLL
512K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 55ns, 70ns
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
– 1.65V--2.2V V
CC
(62WV5128ALL)
– 2.5V--3.6V V
CC
(62WV5128BLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
ISSI
DESCRIPTION
®
PRELIMINARY INFORMATION
MARCH 2002
The
ISSI
IS62WV5128ALL / IS62WV5128BLL are high-
speed, 4M bit static RAMs organized as 512K words by 8
bits. It is fabricated using
ISSI
's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When
CS1
is HIGH (deselected) or when CS2 is LOW
(deselected) or when
CS1
is LOW, CS2 is HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE)
controls both writing and reading of the memory.
The IS62WV5128ALL and IS62WV5128BLL are packged in
the JEDEC standard 32-pin TSOP (TYPE I), 32-pin sTSOP
(TYPE I), 32-pin TSOP (TypeII), and 36-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 8
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CS2
CS1
OE
WE
CONTROL
CIRCUIT
ISSI reserves the right to make changes this specification herein and it products at any time without notice. ISSI assumes no responsibility or liability arising out of the application or use of any information,
product or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
© Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
03/11/02
1

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