a
FEATURES
100 MSPS Wideband Inputs (14 Linear Bits Plus 3 RSSI)
Dual High-Speed Data Input Ports
Four Independent Digital Receivers in Single Package
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
Programmable Attenuator Control for Clip Prevention
and External Gain Ranging via Level Indicator
Flexible Control for Multicarrier and Phased Array
3.3 V I/O, 2.5 V CMOS Core
User-Configurable Built-In Self-Test (BIST) Capability
JTAG Boundary Scan
APPLICATIONS
Multicarrier, Multimode Digital Receivers GSM, IS136,
EDGE, PHS, IS95
Micro and Pico Cell Systems
Wireless Local Loop
Smart Antenna Systems
Software Radios
In-Building Wireless Telephony
PRODUCT DESCRIPTION
Four-Channel, 100 MSPS Digital
Receive Signal Processor (RSP)
AD6624A
The AD6624A is part of Analog Devices’ SoftCell
®
multicarrier
transceiver chipset designed for compatibility with Analog
Devices’ family of high sample rate IF sampling ADCs (AD6640/
AD6644 12- and 14-bit). The SoftCell receiver comprises a
digital receiver capable of digitizing an entire spectrum of
carriers and digitally selecting the carrier of interest for tuning
and channel selection. This architecture eliminates redundant
radios in wireless base station applications.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies less
bandwidth than the input signal, this rejection of out-of-band
noise is called “processing gain.” By using large decimation
factors, this “processing gain” can improve the SNR of the
ADC by 30 dB or more. In addition, the programmable RAM
coefficient filter allows antialiasing, matched filtering, and
static equalization functions to be combined in a single, cost-
effective filter.
The AD6624A is compatible with standard ADC converters such
as the AD664x, AD9042, AD943x and the AD922x families of
data converters. The AD6624A is also compatible with the
AD6600 Diversity ADC, providing a cost and size reduction path.
The AD6624A is a four-channel (quad) digital receive signal
processor (RSP) with four cascaded signal-processing elements:
a frequency translator, two fixed-coefficient decimating filters,
and a programmable-coefficient decimating filter.
FUNCTIONAL BLOCK DIAGRAM
16 BITS
INA[13:0]
EXPA[2:0]
IENA
LIA-A
LIA-B
SYNCA
SYNCB
SYNCC
SYNCD
INB[13:0]
EXPB[2:0]
IENB
LIB-A
LIB-B
CH D
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
INPUT
MATRIX
CH C
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
CH B
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
18 BITS
20 BITS
RAM
COEFFICIENT
FILTER
24 BITS
SDIN[3:0]
SDO[3:0]
DR[3:0]
SDFS[3:0]
SDFE[3:0]
SCLK[3:0]
MODE
DS(RD)
CS
RW(WR)
DTACK(RDY)
A[2:0]
D[7:0]
CH A
NCO
rCIC2
RESAMPLER
CIC5
SERIAL
AND
MICROPORT
EXTERNAL SYNC
CIRCUITRY
JTAG
INTERFACE
BUILT-IN
SELF-TEST
SoftCell is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD6624A
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS/CHARACTERISTICS . . . . . . . . . . . . . . . . 3
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . 9
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . 11
ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EXAMPLE FILTER RESPONSE . . . . . . . . . . . . . . . . . . . . . . 14
INPUT DATA PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Gain Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input Data Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Scaling with Fixed-Point ADCs . . . . . . . . . . . . . . . . . . . . . . . 16
Scaling with Floating-Point or Gain-Ranging ADCs . . . . . . . 16
NUMERICALLY CONTROLLED OSCILLATOR . . . . . . . . 17
Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
NCO Frequency Hold-Off Register . . . . . . . . . . . . . . . . . . . . 17
Serial Ports Cascaded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Output Frame Timing (Master and Slave) . . . . . . . . . .
Serial Port Timing Specifications . . . . . . . . . . . . . . . . . . . . . .
SBM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Word Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDFS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mapping RCF Data to the BIST Registers . . . . . . . . . . . . . .
0x00–0x7F: Coefficient Memory (CMEM) . . . . . . . . . . . . . .
0x80: Channel Sleep Register . . . . . . . . . . . . . . . . . . . . . . . .
0x81: Soft_SYNC Register . . . . . . . . . . . . . . . . . . . . . . . . . .
0x82: Pin_SYNC Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x83: Start Hold-Off Counter . . . . . . . . . . . . . . . . . . . . . . . .
0x84: NCO Frequency Hold-Off Counter . . . . . . . . . . . . . .
0x85: NCO Frequency Register 0 . . . . . . . . . . . . . . . . . . . . .
0x86: NCO Frequency Register 1 . . . . . . . . . . . . . . . . . . . . .
0x87: NCO Phase Offset Register . . . . . . . . . . . . . . . . . . . . .
0x88: NCO Control Register . . . . . . . . . . . . . . . . . . . . . . . . .
0x90: rCIC2 Decimation – 1 (M
rCIC2
–1) . . . . . . . . . . . . . . . .
0x91: rCIC2 Interpolation – 1 (L
rCIC2
–1) . . . . . . . . . . . . . . .
0x92: rCIC2 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x93: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x94: CIC5 Decimation – 1 (M
CIC5
–1) . . . . . . . . . . . . . . . . .
0x95: CIC5 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x96: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0xA0: RCF Decimation – 1 (M
RCF
–1) . . . . . . . . . . . . . . . . . .
0xA1: RCF Decimation Phase (P
RCF
) . . . . . . . . . . . . . . . . . .
0xA2: RCF Number of Taps Minus One (N
RCF
-1) . . . . . . . .
0xA3: RCF Coefficient Offset (CO
RCF
) . . . . . . . . . . . . . . . . .
0xA4: RCF Control Register . . . . . . . . . . . . . . . . . . . . . . . . .
0xA5: BIST Register for I . . . . . . . . . . . . . . . . . . . . . . . . . . .
0xA6: BIST Register for Q . . . . . . . . . . . . . . . . . . . . . . . . . .
0xA7: BIST Control Register . . . . . . . . . . . . . . . . . . . . . . . .
0xA8: RAM BIST Control Register . . . . . . . . . . . . . . . . . . .
0xA9: Serial Port Control Register . . . . . . . . . . . . . . . . . . . .
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Access Control Register (ACR) . . . . . . . . . . . . . . . . . . . . . . .
External Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Address Register (CAR) . . . . . . . . . . . . . . . . . . . . . .
SOFT_SYNC Control Register . . . . . . . . . . . . . . . . . . . . . . .
PIN_SYNC Control Register . . . . . . . . . . . . . . . . . . . . . . . . .
SLEEP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read/Write Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel Nonmultiplexed Mode (INM) . . . . . . . . . . . . . . . . . . . .
Motorola Nonmultiplexed Mode (MNM) . . . . . . . . . . . . . . .
Input Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERNAL WRITE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . .
Write Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERNAL READ ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
28
29
29
29
29
29
29
29
29
30
30
30
30
30
30
30
30
30
30
30
31
31
31
31
31
31
31
31
31
31
31
31
32
32
32
32
32
33
33
33
34
34
34
34
34
35
35
35
35
35
35
35
36
36
37
37
38
38
39
Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
NCO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Amplitude Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Phase Accumulator on HOP . . . . . . . . . . . . . . . . . . . . .
Input Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 00: Blank On IEN Low . . . . . . . . . . . . . . . . . . . . . . . .
Mode 01: Clock On IEN High . . . . . . . . . . . . . . . . . . . . . . .
Mode 10: Clock on IEN Transition to High . . . . . . . . . . . . .
Mode 11: Clock on IEN Transition to Low . . . . . . . . . . . . . .
WB Input Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sync Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECOND ORDER rCIC FILTER . . . . . . . . . . . . . . . . . . . . . .
rCIC2 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Decimation and Interpolation Registers . . . . . . . . . . . . . . . . .
rCIC2 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFTH ORDER CASCADED INTEGRATOR COMB
FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CIC5 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . . . . .
RCF Decimation Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
RCF Decimation Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RCF Filter Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RCF Output Scale Factor and Control Register . . . . . . . . . .
USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST) . .
RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHANNEL BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHIP SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . .
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . .
Serial Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . .
Compact Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Data Frame (Serial Bus Master) . . . . . . . . . . . . . . . . . .
Serial Data Frame (Serial Cascade) . . . . . . . . . . . . . . . . . . . .
Configuring the Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Port Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Port to DSP Interconnection . . . . . . . . . . . . . . . . . . . .
Serial Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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REV. 0
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