PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES
Fast Throughput Rate: 1MSPS
Specified for V
DD
of 2.7 V to 5.25 V
Low Power at max Throughput Rate:
3.75 mW typ at 1MSPS with V
DD
= 3 V
9 mW typ at 1MSPS with V
DD
= 5 V
Pseudo Differential Analog Input
Wide Input Bandwidth:
70dB SINAD at 300kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface - SPI
TM
/QSPI
TM
/
MICROWIRE
T M
/ DSP Compatible
Power-Down Mode: 1µA max
8 Pin SOT-23 and µSOIC Packages
APPLICATIONS
Transducer Interface
Battery Powered Systems
Data Acquisition Systems
Portable Instrumentation
Motor Control
Communications
GENERAL DESCRIPTION
Pseudo Differential, 1MSPS,
12- & 10-Bit ADCs in 8-lead SOT-23
AD7451/AD7441
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN-
VREF
T/H
12-BIT SUCCESSIVE
APPROXIMATION
ADC
SCLK
AD7451/
AD7441
CONTROL
LOGIC
SDATA
+5
GND
The AD7451/AD7441 are respectively 12- and 10-bit,
high speed, low power, successive-approximation (SAR)
analog-to-digital converters that feature a pseudo differen-
tial analog input. These parts operate from a single 2.7 V
to 5.25 V power supply and feature throughput rates up to
1MSPS.
The parts contains a low-noise, wide bandwidth, differen-
tial track and hold amplifier (T/H) which can handle
input frequencies in excess of 1MHz with the -3dB point
being 20MHz typically. The reference voltage is 2.5 V
and is applied externally to the V
REF
pin.
The conversion process and data acquisition are controlled
using
CS
and the serial clock allowing the device to inter-
face with Microprocessors or DSPs. The input signals are
sampled on the falling edge of
CS
and the conversion is
also initiated at this point.
The SAR architecture of these parts ensures that there are
no pipeline delays.
The AD7451/41 use advanced design techniques to achieve
very low power dissipation at high throughput rates.
PRODUCT HIGHLIGHTS
1.Operation with 2.7 V to 5.25 V power supplies.
2.High Throughput with Low Power Consumption.
With a 3V supply, the AD7451/41 offer 3.75mW typ
power consumption for 1MSPS throughput.
3.Pseudo Differential Analog Input.
The V
IN-
input can be used as an offset from ground
4.Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. These
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.
5.No Pipeline Delay.
6.Accurate control of the sampling instant via a
CS
input
and once off conversion control.
MICROWIRE is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
REV. PrC 24/05/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD7451 - SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion)
(SINAD)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise
2
Intermodulation Distortion (IMD)
2
Second Order Terms
Third Order Terms
Aperture Delay
2
Aperture Jitter
2
Full Power Bandwidth
2
DC ACCURACY
Resolution
Integral Nonlinearity (INL)
2
Differential Nonlinearity (DNL)
2
Offset Error
2
Gain Error
2
ANALOG INPUT
Full Scale Input Span
Absolute Input Voltage
V
IN+
V
IN- 3
DC Leakage Current
Input Capacitance
REFERENCE INPUT
V
REF
Input Voltage
DC Leakage Current
V
REF
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
4
Output Coding
1
( V
DD
= 2.7V to 5.25V, f
SCLK
= 18MHz, f
S
= 1MHz, V
REF
= 2.5 V; F
IN
= 300kHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
B Version
1
Unit
Test Conditions/Comments
-80dB typ
-82dB typ
70
-75
-75
-85
-85
10
50
20
2.5
12
±1
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
V
V
V
µA max
pF typ
pF typ
@ -3 dB
@ -0.1 dB
Guaranteed No Missed Codes
to 12 Bits.
±1
±3
±3
V
REF
V
REF
0.1 to 1
±1
20
6
V
IN+
- V
IN-
When in Track
When in Hold
±1% tolerance for
specified performance
2.5
±1
15
2.4
0.8
±1
10
2.8
2.4
0.4
±1
10
Straight
(Natural)
Binary
V
µA max
pF typ
V min
V max
µA max
pF max
V min
V min
V max
µA max
pF max
Typically 10nA, V
IN
= 0VorV
DD
V
DD
= 5V; I
SOURCE
= 200µA
V
DD
= 3V; I
SOURCE
= 200µA
I
SINK
=200µA
–2–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7451 - SPECIFICATIONS
Parameter
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
2
Step Input
Throughput Rate
6
POWER REQUIREMENTS
V
DD
I
DD5,7
Normal Mode(Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down
1
AD7451/AD7441
B Version
1
16
200
TBD
1
Units
SCLK cycles
ns max
ns max
MSPS max
Test Conditions/Comments
888ns with an 18MHz SCLK
Sine Wave Input
TBD
2.7/5.25
SCLK On or Off
V
DD
= 5 V.
V
DD
= 3 V.
SCLK On or Off
V
DD
V
DD
V
DD
V
DD
=5
=3
=5
=3
V.
V.
V. SCLK On or Off
V. SCLK On or Off
0.5
1.8
1.25
1
9
3.75
5
3
Vmin/max
mA typ
mA max
mA max
µA max
mW max
mW max
µW max
µW max
NOTES
1
Temperature ranges as follows: B Versions: –40°C to +85°C.
2
See ‘Terminology’ section.
3
A small DC input is applied to V
IN-
to provide a pseudo ground for V
IN+
4
Sample tested @ +25°C to ensure compliance.
5
See POWER VERSUS THROUGHPUT RATE section.
6
See ‘Serial Interface Section’.
7
Measured with a midscale DC input.
Specifications subject to change without notice.
REV. PrC
–3–
PRELIMINARY TECHNICAL DATA
AD7441 - SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion)
(SINAD)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise
2
Intermodulation Distortion (IMD)
2
Second Order Terms
Third Order Terms
Aperture Delay
2
Aperture Jitter
2
Full Power Bandwidth
2
DC ACCURACY
Resolution
Integral Nonlinearity (INL)
2
Differential Nonlinearity (DNL)
2
Offset Error
Gain Error
2
2
1
( V
DD
= 2.7V to 5.25V, f
SCLK
= 18MHz, f
S
= 1MHz, V
REF
= 2.5 V; F
IN
= 300kHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
B Version
1
Unit
Test Conditions/Comments
-80dB typ
-82dB typ
61
-73
-73
-78
-78
10
50
20
2.5
10
±0.5
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
V
V
V
µA max
pF typ
pF typ
@ -3 dB
@ -0.1 dB
Guaranteed No Missed Codes
to 10 Bits.
±0.5
±3
±3
V
REF
V
REF
0.1 to 1
±1
20
6
ANALOG INPUT
Full Scale Input Span
Absolute Input Voltage
V
IN+
V
IN- 3
DC Leakage Current
Input Capacitance
REFERENCE INPUT
V
REF
Input Voltage
DC Leakage Current
V
REF
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
4
Output Coding
V
IN+
- V
IN-
When in Track
When in Hold
±1% tolerance
for specified performance
2.5
±1
15
2.4
0.8
±1
10
2.8
2.4
0.4
±1
10
Straight
(Natural)
Binary
V
µA max
pF typ
V min
V max
µA max
pF max
V min
V min
V max
µA max
pF max
Typically 10nA, V
IN
= 0VorV
DD
V
DD
= 5V; I
SOURCE
= 200µA
V
DD
= 3V; I
SOURCE
= 200µA
I
SINK
=200µA
–4–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7441 - SPECIFICATIONS
1
Parameter
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
2
Throughput Rate
6
POWER REQUIREMENTS
V
DD
I
DD6,7
Normal Mode(Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down
Test Conditions/Comments
888ns with an 18MHz SCLK
Sine Wave Input
Step Input
B Version
1
16
200
TBD
1
AD7451/AD7441
Units
SCLK cycles
ns max
ns max
MSPS max
2.7/5.25
SCLK On or Off
V
DD
= 5 V.
V
DD
= 3 V.
SCLK On or Off
V
DD
V
DD
V
DD
V
DD
=5
=3
=5
=3
V.
V.
V. SCLK On or Off
V. SCLK On or Off
0.5
1.8
1.25
1
9
3.75
5
3
Vmin/max
mA typ
mA max
mA max
µA max
mW max
mW max
µW max
µW max
NOTES
1
Temperature ranges as follows: B Versions: –40°C to +85°C.
2
See ‘Terminology’ section.
3
A small DC input is applied to V
IN-
to provide a pseudo ground for V
IN+
4
Sample tested @ +25°C to ensure compliance.
5
See POWER VERSUS THROUGHPUT RATE section.
6
See ‘Serial Interface Section’.
7
Measured with a midscale DC input.
Specifications subject to change without notice.
REV. PrC
–5–
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