CS4953xx Data Sheet
FEATURES
Multi-standard 32-bit Audio Decoding plus Post
processing
Supports legacy audio formats and a wide array of post-
processing
— Dolby Digital
®
EX, Dolby Pro Logic
®
II, IIx, IIz 7.1,
Dolby Headphone 2
®
, Dolby Virtual Speaker 2
®
,
Dolby Volume
®
(original), Dolby Volume 258 (lite),
Audistry
®
— DTS-ES 96/24
™
Discrete 7.1, DTS-ES
™
Discrete 7.1,
DTS-ES
™
Matrix 6.1, DTS Neo:6
®
, DTS Neural
Surround
™
DTS Surround Sensation Speaker
— MPEG-2 AAC
™
LC 5.1
— SRS
®
Circle Surround II
®
, SRS Circle Surround Auto,
SRS Circle Surround Decoder Optimized, SRS
TruVolume
™
7.1 (V 2.1.0.0), SRS TruSurround
HD/HD4
®
, SRS WOW HD
™
, SRS CS Headphone
™
,
SRS Circle Cinema 3D
™
, SRS Studio Sound HD
™
— THX
®
Ultra2
™
, THX Select2
™
Cirrus Logic’s Applications Library
— Cirrus Original Multi-Channel Surround 2 (COMS2),
Cirrus Band XpandeR
™
, Cirrus Virtualization
Technology (CVT), Cirrus Intelligent Room Calibration
2 (IRC2), Cirrus Bass Enhancement (CBE)
— Crossbar Mixer, Signal Generator
— Advanced Post-Processors including: 7.1 Bass
Manager Quadruple Crossover, Tone Control, 11-
Band Parametric EQ, Delay, 2:1/4:1 Decimator,
1:2/1:4 Upsampler
Up to 12 Channels of 32-bit Serial Audio Input
Audio Decoder DSP Family with
Dual 32-bit DSP Engine Technology
16 Ch x 32-bit PCM Out with Dual 192 kHz S/PDIF Tx
Two SPI
™
/I
2
C
™
Ports
Customer Software Security Keys
Large On-chip X, Y, and Program RAM & ROM
SDRAM and Serial Flash Memory Support
The CS4953xx DSP family are the enhanced versions of the
CS495xx DSP family with higher overall performance and
lower system cost. The CS4953xx includes all mainstream
audio processing codes in on-chip ROM. This saves external
memory for code storage. In addition, the intensive decoding
tasks of Dolby Digital Surround EX
®
, AAC multi-channel,
DTS-ES 96/24, THX Ultra2 Cinema and Dolby Headphone
can be accomplished without the expense of external
SDRAM memory.
With larger internal memories than the CS495xx, the
CS49531x is designed to support up to 150 ms per channel
of lip-sync delay. With 150 MHz internal clock speed, the
CS4953xx supports the most demanding post-processing
requirements. It is also designed for easy upgrading.
Customers currently using the CS495xx can upgrade to the
CS4953xx with minor hardware and software changes.
Ordering Information
See
page 27
for ordering information.
Serial
Control 1
12 Ch PCM
Audio In
Serial
Control 2
Parallel
Control
GPIO
Debug
STC
Coyote 32-bit
DSP A
D
M
A
Coyote 32-bit
DSP B
P
X
Y
TMR1
TMR2
S/PDIF S/PDIF
16 Ch PCM
Audio Out
P
X
Y
Ext. Memory Controller
PLL
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
April 2011
DS705PP8
http://www.cirrus.com
Copyright © 2011 Cirrus Logic, Inc.
All Rights Reserved
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
Table of Contents
1 Documentation Strategy ............................................................................................................4
2 Overview .....................................................................................................................................4
2.1 Migrating from CS495xx(2) to CS4970x4 ................................................................................................. 5
2.2 Licensing .................................................................................................................................................. 5
3 Code Overlays ............................................................................................................................6
4 Hardware Functional Description ............................................................................................6
4.1 Coyote DSP Core ..................................................................................................................................... 6
4.1.1 DSP Memory ...............................................................................................................................6
4.1.2 DMA Controller ............................................................................................................................7
4.2 On-chip DSP Peripherals ......................................................................................................................... 7
4.2.1 Digital Audio Input Port (DAI) .......................................................................................................7
4.2.2 Digital Audio Output Port (DAO) ..................................................................................................7
4.2.3 Serial Control Port 1 & 2 (I
2
C™ or SPI™) ...................................................................................7
4.2.4 Parallel Control Port ....................................................................................................................7
4.2.5 External Memory Interface ..........................................................................................................7
4.2.6 General Purpose Input/Output (GPIO) ........................................................................................7
4.2.7 Phase-locked Loop (PLL)-based Clock Generator ......................................................................8
4.3 DSP I/O Description ................................................................................................................................. 8
4.3.1 Multiplexed Pins ..........................................................................................................................8
4.3.2 Termination Requirements ...........................................................................................................8
4.3.3 Pads ............................................................................................................................................8
4.4 Application Code Security ........................................................................................................................ 8
5 Characteristics and Specifications ..........................................................................................8
5.1 Absolute Maximum Ratings ...................................................................................................................... 8
5.2 Recommended Operating Conditions ...................................................................................................... 9
5.3 Digital DC Characteristics ........................................................................................................................ 9
5.4 Power Supply Characteristics .................................................................................................................. 9
5.5 Thermal Data (144-Pin LQFP) ............................................................................................................... 10
5.6 Thermal Data (128-pin LQFP) ................................................................................................................ 10
5.7 Switching Characteristics—
RESET
......................................................................................................... 11
5.8 Switching Characteristics — XTI ............................................................................................................ 11
5.9 Switching Characteristics — Internal Clock ............................................................................................ 12
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode ..................................................... 12
5.11 Switching Characteristics — Serial Control Port - SPI Master Mode ................................................... 13
5.12 Switching Characteristics — Serial Control Port - I
2
C Slave Mode ...................................................... 14
5.13 Switching Characteristics — Serial Control Port - I
2
C Master Mode .................................................... 15
5.14 Switching Characteristics — Parallel Control Port - Intel Slave Mode ................................................. 16
5.15 Switching Characteristics — Parallel Control Port - Motorola Slave Mode ......................................... 18
5.16 Switching Characteristics — Digital Audio Slave Input Port ................................................................. 20
5.17 Switching Characteristics — Digital Audio Output Port ........................................................................ 21
5.18 Switching Characteristics — SDRAM Interface .................................................................................... 22
6 Ordering Information ...............................................................................................................25
7 Environmental, Manufacturing, and Handling Information .................................................26
8 Device Pin-Out Diagram ..........................................................................................................27
8.1 128-Pin LQFP Pin-Out Diagram ............................................................................................................. 27
8.2 144-Pin LQFP Pin-Out Diagram ............................................................................................................ 28
9 Package Mechanical Drawings ...............................................................................................29
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
9.1 128-Pin LQFP Package Drawing ........................................................................................................... 29
9.2 144-Pin LQFP Package Drawing ........................................................................................................... 30
10 Revision History .....................................................................................................................31
List of Figures
Figure 1. RESET Timing ........................................................................................................................................12
Figure 2. XTI Timing ..............................................................................................................................................12
Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................14
Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................15
Figure 5. Serial Control Port - I2C Slave Mode Timing ..........................................................................................16
Figure 6. Serial Control Port - I2C Master Mode Timing ........................................................................................17
Figure 7. Parallel Control Port - Intel® Slave Mode Read Cycle ...........................................................................19
Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle ..............................................................................19
Figure 9. Parallel Control Port - Motorola® Slave Mode Read Cycle Timing ........................................................21
Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing .........................................................21
Figure 11. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................22
Figure 12. DAI Slave Timing Diagram ...................................................................................................................22
Figure 13. Digital Audio Port Output Timing Master Mode .....................................................................................23
Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) ...........................................24
Figure 15. External Memory Interface - SDRAM Burst Read Cycle .......................................................................25
Figure 16. External Memory Interface - SDRAM Burst Write Cycle .......................................................................25
Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle ....................................................................26
Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................26
Figure 19. 128-pin LQFP Pin-Out Drawing (CS495303/CS495313) ......................................................................29
Figure 20. 128-pin LQFP Pin-Out Drawing (CS495304/CS495314) ......................................................................30
Figure 21. 144-pin LQFP Pin-Out Drawing (CS495313) ........................................................................................31
Figure 22. 128-pin LQFP Package Drawing .........................................................................................................32
Figure 23. 144-pin LQFP Package Drawing .........................................................................................................33
List of Tables
Table 1. CS4953xx Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. CS49530x DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. CS49531x DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6. Environmental, Manufacturing, and Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. 128-pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. 144-pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
1 Documentation Strategy
The CS4953xx data sheet describes the CS4953xx family of multichannel audio decoders. This document
should be used in conjunction with the following documents when evaluating or designing a system around the
CS4953xx family of processors.
Table 1. CS4953xx Related Documentation
Document Name
CS4953xx Data Sheet
Description
This document, which contains the hardware
specifications for the CS4953xx family
Includes detailed system design information for
CS4953x3 product family, including Typical
Connection Diagrams, Boot-Procedures, Pin
Descriptions, etc.
A new consolidated documentation set for the
CS4953x4 product family that includes:
• Detailed system design information including typical
connection diagrams, boot procedures, pin
descriptions, etc. Also describes use of DSP
condenser tool
• Detailed firmware design information including
signal processing flow diagrams and control API
information
AN288 -
CS4953xx/CS4970x4 Firmware User’s Manual
Includes detailed firmware design information
including signal processing flow diagrams and control
API information
CS4953xx Hardware User’s Manual
CS495314/CS4970x4 System Designer’s Guide
The scope of the CS4953xx data sheet is primarily the hardware specifications of the CS4953xx family of
devices. This includes hardware functionality, characteristic data, pinout, and packaging information.
The intended audience for the CS4953xx data sheet is the system PCB designer, MCU programmer, and the
quality control engineer.
2 Overview
The CS4953xx DSP Family, together with Cirrus Logic’s comprehensive library of audio processing algorithms
enables the development of next-generation audio solutions. There are two classes of devices in the
CS4953xx DSP family:
• CS4953x3 Class (ROM ID 3), comprising the CS495303 and the CS495313
• CS4953x4 Class (ROM ID 4), comprising the CS495304 and the CS495314
The primary difference between the CS4953x3 and the CS4953x4 classes is the support of the DSP
Condenser application on the CS4953x4 class of products only. The DSP Condenser is a tool set that enables
the DSP to automatically boot and configure itself from an external serial FLASH, thus reducing the traditional
heavy loading on the part of the system microcontroller. Because of the design time savings, enhanced tools
support, and better performance associated with the CS4953x4 product set, Cirrus Logic recommends that the
CS4953x4 family be used for all new designs. More information on the DSP Condenser can be found in the
CS4953x4/CS497xx System Designer’s Guide.
Within each ROM ID class (3, 4), the breakdown into two devices per class (CS49530x and CS49531x) is
based on the differences between the internal memory size and DSP firmware supported. Essentially, the
audio processing features of the CS49531x are a superset of audio features available in the CS49530x.
Table 2, “Device and Firmware Selection Guide,” on page 6
provides details of the differences between the two
product classes.
Note:
The CS495303/04/14 is available in a 128-pin LQFP package and the CS495313 is available in a 128-pin
or 144-pin LQFP package.
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
2.1 Migrating from CS4953x3 to CS4953x4
• The recommended way to boot the DSP for normal operation is “master boot”. Refer to Chapter 1 of the
CS4953x4/CS4970x4 System Designer’s Guide.
CS4953x4 supports slave boot mode as well (used for
programming the serial flash with the DSP code, through the SCP2 port).
• CS4953x4 DSPs are only available in 128 pin package.
• The serial flash chip select pin used is pin 14 (GPIO0) for master boot. Cirrus Logic recommends that at
least an 8-Mb serial flash device be used. Refer to
CS4953x4/CS4970x4 System Designer’s Guide
for a
list of flash types that are currently supported.
• CS4953x4 DSP family supports DSP Condenser and DSP Manager API for runtime control/host
communication. Refer to
CS4953x4/CS4970x4 System Designer’s Guide
for details.
2.2 Licensing
Licenses are required for all third party audio decoding/processing algorithms, including the application notes.
contact your local Cirrus Sales representative for more information.
3 Code Overlays
The suite of software available for the CS4953xx family consists of an operating system (OS) and a library of
overlays. The overlays have been divided into three main groups called Decoders, Matrix-processors, and
Post-processors. All software components are defined below:
•
OS/Kernel
- Encompasses all non-audio processing tasks, including loading data from external memory,
processing host messages, calling audio-processing subroutines, error concealment, etc.
•
Decoders
- Any Module that initially writes data into the audio I/O buffers, e.g. AC-3
™
, DTS, PCM, etc. All
the decoding/processing algorithms listed below require delivery of PCM or IEC61937-packed,
compressed data via I
2
S- or LJ-formatted digital audio to the CS4953xx.
•
Matrix-processors
- Any module that processes audio I/O buffer PCM data in-place before the Post-
processors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer
through processes like Virtualization (n2 channels) or Matrix Decoding (2n channels). Examples are
Dolby ProLogic II, IIx, IIz and DTS Neo:6.
•
Post-processors
- Any module that processes audio I/O buffer PCM data in-place after the Matrix-
Processors. Examples are Bass Management, Audio Manager, Tone Control, EQ, Delay, Customer-
specific Effects, Dolby Headphone
®
2 and Dolby Virtual Speaker
®
2, etc.
The overlay structure reduces the time required to reconfigure the DSP when a processing change is
requested. Each overlay can be reloaded independently without disturbing the other overlays. For example,
when a new decoder is selected, the OS, matrix-, and post-processors do not need to be reloaded — only the
new decoder (the same is true for the other overlays).
Table 2
below lists the firmware available based on device selection. Refer to AN288,
CS4953xx/CS497xxx
Firmware User’s Manual
for the latest listing of application codes and Cirrus Framework
™
modules available.
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Microcontroller MCU
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