150 MSPS Wideband
Digital Down-Converter (DDC)
AD6636
FEATURES
4/6 independent wideband processing channels
Processes 6 wideband carriers (UMTS, CDMA2000)
4 single-ended or 2 LVDS parallel input ports
(16 linear bit plus 3-bit exponent) running at 150 MHz
Supports 300 MSPS input using external interface logic
3 16-bit parallel output ports operating up to 200 MHz
Real or complex input ports
Quadrature correction and dc correction for complex inputs
Supports output rate up to 34 MSPS per channel
RMS/peak power monitoring of input ports
Programmable attenuator control for external gain ranging
3 programmable coefficient FIR filters per channel
2 decimating half-band filters per channel
6 programmable digital AGC loops with 96 dB range
Synchronous serial I/O operation (SPI®-, SPORT-compatible)
Supports 8-bit or 16-bit microport modes
3.3 V I/O, 1.8 V CMOS core
User-configurable built-in self-test (BIST) capability
JTAG boundary scan
APPLICATIONS
Multicarrier, multimode digital receivers
GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, TD-SCDMA
Micro and pico cell systems, software radios
Broadband data applications
Instrumentation and test equipment
Wireless local loop
In-building wireless telephony
FUNCTIONAL BLOCK DIAGRAM
CLKA
NCO
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
INPUT MATRIX
ADC A/AI
EXPA [2:0]
NCO
CIC5
M = 1-32
CLKB
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
DATA ROUTING
AGC
PA
EXPB [2:0]
CMOS
REAL
PORTS
A, B,
C,D
NCO
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
DATA ROUTER MATRIX
ADC B/AQ
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
CLKC
PB
ADC C/CI
NCO
CMOS
EXPC [2:0] COMPLEX
PORTS
(AI, AQ)
CLKD (BI, BQ)
LVDS
PORTS
AB, CD
PEAK/
RMS
MEAS.
I,Q
CORR.
NCO
NCO
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
PARALLEL PORTS
PC
ADC D/CQ
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
EXPD [2:0]
______
RESET
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
SYNC [3:0]
NOTE: CHANNELS RENDERED AS
ARE AVAILABLE ONLY IN 6-CHANNEL PART
M = DECIMATION
L = INTERPOLATION
Figure 1.
Rev. 0
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Tel: 781.329.4700
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Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
04998-0-001
PLL CLOCK
MULTIPLIER
16-BIT
MICROPORT INTERFACE
SPORT/SPI INTERFACE
JTAG
AD6636
TABLE OF CONTENTS
Product Description......................................................................... 3
Product Highlights ....................................................................... 4
Specifications..................................................................................... 5
Electrical Characteristics ............................................................. 5
General Timing Characteristics ................................................. 6
Microport Timing Characteristics ............................................. 7
Serial Port Timing Characteristics ............................................. 8
Explanation of Test Levels for Specifications............................ 8
Absolute Maximum Ratings............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Pin Listing for Power, Ground, Data and Address Buses ...... 12
Timing Diagrams............................................................................ 13
Theory of Operation ...................................................................... 19
ADC Input Port .......................................................................... 19
PLL Clock Multiplier ................................................................. 20
ADC Gain Control ..................................................................... 21
ADC Input Port Monitor Function.......................................... 22
Quadrature I/Q Correction Block............................................ 24
Input Crossbar Matrix ............................................................... 26
Numerically Controlled Oscillator (NCO) ............................. 26
Fifth-Order CIC Filter ............................................................... 28
FIR Half-Band Block.................................................................. 29
Intermediate Data Router ......................................................... 32
Mono-Rate RAM Coefficient Filter (MRCF) ......................... 32
Decimating RAM Coefficient Filter (DRCF) ........................ 33
Channel RAM Coefficient Filter (CRCF) ............................... 35
Interpolating Half-Band Filter.................................................. 36
Output Data Router ................................................................... 37
Automatic Gain Control............................................................ 39
Parallel Port Output ................................................................... 43
User-Configurable Built-In Self-Test (BIST) .......................... 47
Chip Synchronization ................................................................ 47
Serial Port Control ..................................................................... 48
Microport .................................................................................... 52
JTAG Boundary Scan................................................................. 53
Memory Map .................................................................................. 54
Reading the Memory Map Table.............................................. 54
Global Register Map .................................................................. 56
Input Port Register Map ............................................................ 59
Channel Register Map ............................................................... 62
Output Port Register Map ......................................................... 67
Design Notes ................................................................................... 70
Outline Dimensions ....................................................................... 72
Ordering Guide .......................................................................... 72
REVISION HISTORY
8/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 72
AD6636
PRODUCT DESCRIPTION
The AD6636 is a digital down-converter intended for IF
sampling or oversampled baseband radios requiring wide-
bandwidth input signals. Optimized for the demanding filtering
requirements of wideband standards, such as CDMA2000,
UMTS, and TD-SCDMA, the AD6636 is designed for radio
systems that use either an IF sampling ADC or a baseband
sampling ADC.
The AD6636 channels have the following signal processing
stages: a frequency translator, a fifth-order cascaded integrated
comb filter, two sets of cascaded fixed-coefficient FIR and half-
band filters, three cascaded programmable coefficient sum-of-
product FIR filters, an interpolating half-band filter (IHB), and
a digital automatic gain control (AGC) block. Multiple modes
are supported for clocking data into and out of the chip and
provide flexibility for interfacing to a wide variety of digitizers.
Programming and control are accomplished via serial or
microport interfaces.
Input ports can take input data at up to 150 MSPS. Up to
300 MSPS input data can be supported using two input ports
(some external interface logic is required) and two internal
channels processing in tandem. Biphase filtering in output data
router is selected to complete the combined filtering mode. The
four input ports can operate in CMOS mode, or two ports can
be combined for LVDS input mode. The maximum input data
rate for each input port is 150 MHz.
Frequency translation is accomplished with a 32-bit complex
numerically controlled oscillator (NCO). It has greater than
110 dBc SDFR. This stage translates either a real or complex
input signal from IF (intermediate frequency) to a baseband
complex digital output. Phase and amplitude dither can be
enabled on-chip to improve spurious performance of the NCO.
A 16-bit phase-offset word is available to create a known phase
relationship between multiple AD6636 chips or channels. The
NCO also can be bypassed so that baseband I and Q inputs can
be provided directly from baseband sampling ADC through
input ports.
Following frequency translation is a fifth-order CIC filter with a
programmable decimation between 1 and 32. This filter is used
to lower the sample rate efficiently, while providing sufficient
alias rejection at frequencies with higher frequency offsets from
the signal of interest.
Following the CIC5 are two sets of filters. Each set has a non-
decimating FIR filter and a decimate-by-2 half-band filter. The
FIR1 filter provides about 30 dB of rejection, while the HB1
filter provides about 77 dB of rejection. They can be used
together to achieve a 107 dB stopband alias rejection, or they
can be individually bypassed to save power. The FIR2 filter
provides about 30 dB of rejection, while the HB2 filter provides
about 65 dB of rejection. The filters can be used either together
to achieve more than 95 dB stopband alias rejection, or can be
individually bypassed to save power. FIR1 and HB1 filters can
run with a maximum input rate of 150 MSPS. In contrast, FIR2
and HB2 can run with a maximum input rate of 75 MSPS
(input rate to FIR2 and HB2 filters).
The programmable filtering is divided into three cascaded RAM
coefficient filters (RCFs) for flexible and power efficient
filtering. The first filter in the cascade is the MRCF, consisting
of a programmable nondecimating FIR. It is followed by
programmable FIR filters (DRCF) with decimation from 1
to 16. They can be used either together to provide high rejection
filters, or independently to save power. The maximum input rate
to the MRCF is one-fourth of PLL clock rate.
The CRCF (Channel RCF) is the last programmable FIR filter
with programmable decimation from 1 to 16. It typically is used
to meet the spectral mask requirements for the air standard of
interest. This could be an RRC, anti-aliasing filter or any other
real data filter. Decimation in preceding blocks is used to keep
the input rate of this stage as low as possible for the best filter
performance.
The last filter stage in the chain is an interpolate-by-2 half-band
filter, which is used to up-sample the CRCF output to produce
higher output oversampling. Signal rejection requirements for
this stage are relaxed because preceding filters already have
filtered the blockers and adjacent carriers.
Each input port of the AD6636 has its own clock used for
latching onto the input data, but Input Port A clock (CLKA) is
used also as the input for an on-board PLL clock multiplier. The
output of the PLL clock is used for processing all filters and
processing blocks beyond the data router following CIC filter.
The PLL clock can be programmed to have a maximum clock
rate of 200 MHz.
A data routing block (DR) is used to distribute data from the
CICs to the various channel filters. This block allows multiple
back end filter chains to work together to process high
bandwidth signals or to make even sharper filter transitions
than a single channel can perform. It also can allow complex
filtering operations to be achieved in the programmable filters.
The digital AGC provides the user with scaled digital outputs
based on the rms level of the signal present at the output of the
digital filters. The user can set the requested level and time
constant of the AGC loop for optimum performance of the
postprocessor. This is a critical function in the base station for
CDMA applications where the power level must be well
controlled going into the RAKE receivers. It has programmable
clipping and rounding control to provide different output
resolutions.
Rev. 0 | Page 3 of 72
AD6636
The overall filter response for the AD6636 is the composite of
all the combined filter stages. Each successive filter stage is
capable of narrower transition bandwidths, but requires a
greater number of CLK cycles to calculate the output. More
decimation in the first filter stage minimizes overall power
consumption. Data from the device is interfaced to a
DSP/FPGA/baseband processor via either high speed parallel
ports (preferred) or a DSP-compatible microprocessor interface.
The AD6636 is available both in 4-channel and 6-channel
versions. The data sheet primarily discusses the 6-channel part.
The only difference between the 6-channel and 4-channel
devices is that on the 4-channel version, Channels 4 and 5 are
not available (see Figure 1). The 4-channel device still has the
same input ports, output ports, and memory map. The memory
map section for Channels 4 and 5 can be programmed and read
back, but it serves no purpose.
PRODUCT HIGHLIGHTS
•
•
•
•
•
Six independent digital filtering channels
101 dB SNR noise performance, 110 dB spurious
performance
Four input ports capable of 150 MSPS input data rates
RMS/peak power monitoring of input ports and 96 dB
range AGCs before the output ports
Three programmable RAM coefficient filters, three half-
band filters, two fixed coefficient filters, and one fifth-order
CIC filter per channel
Complex filtering and biphase filtering (300 MSPS ADC
input) by combining filtering capability of multiple
channels
Three 16-bit parallel output ports operating at up to
200 MHz clock
Blackfin®- and TigerSHARC®-compatible 16-bit
microprocessor port
Synchronous serial communications port is compatible
with most serial interface standards, SPORT, SPI, and SSR
•
•
•
•
Rev. 0 | Page 4 of 72
AD6636
SPECIFICATIONS
Table 1. Recommended Operating Conditions
Parameter
VDDCORE
VDDIO
T
AMBIENT
Temp
Full
Full
Full
Test Level
IV
IV
IV
Min
1.7
3.0
−40
Typ
1.8
3.3
+25
Max
1.9
3.6
+85
Unit
V
V
°C
ELECTRICAL CHARACTERISTICS
Table 2. Electrical Characteristics
1
Parameter
LOGIC INPUTS (NOT 5 V TOLERANT)
Logic Compatibility
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
LOGIC OUTPUTS
Logic Compatibility
Logic 1 Voltage (I
OH
= 0.25 mA)
Logic 0 Voltage (I
OL
= 0.25 mA)
SUPPLY CURRENTS
WCDMA (61.44 MHz) Example
1
I
VDDCORE
I
VDDIO
CDMA 2000 (61.44 MHz) Example
1
I
VDDCORE
I
VDDIO
TDS-CDMA (76.8 MHz) Example
1, 2
I
VDDCORE
I
VDDIO
GSM (65 MHz) Example
1, 2
I
VDDCORE
I
VDDIO
TOTAL POWER DISSIPATION
WCDMA (61.44 MHz)
1
CDMA 2000 (61.44 MHz)
1
TDS-CDMA, (76.8 MHz)
1, 2
GSM, (65 MHz)
1, 2
Temp
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
V
IV
IV
IV
Min
3.3
2.0
−0.3
1
1
4
3.3
2.0
Typ
Max
Unit
V CMOS
V
V
µA
µA
pF
V CMOS
V
V
3.6
+0.8
10
10
VDDIO − 0.2
0.2
0.4
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
V
V
V
V
V
V
V
V
V
V
V
V
V
450
50
400
25
250
15
175
10
975
800
500
350
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
1
2
One input port, all six channels, and the relevant signal processing blocks are active.
PLL is turned off for power savings.
Rev. 0 | Page 5 of 72
Embedded System
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