FUJITSU SEMICONDUCTOR
DATA SHEET
DS04–21348–3E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip prescaler
MB15C02
s
DESCRIPTION
The Fujitsu MB15C02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a prescaler. A 64/65
division is available for the prescaler that enables pulse swallow operation.
This operates with a supply voltage of 1.0 V (min.).
MB15C02 is suitable for mobile communications, such as paging systems.
s
FEATURES
• High frequency operation: 220 MHz max @V
DD
= 1.0 V to 1.5 V
330 MHz max @V
DD
= 1.2 V to 1.5 V
450 MHz max @V
DD
= 1.3 V to 1.5 V
• Single power supply : V
DD
= 1.0 to 1.5 V
• Power saving function
• Pulse swallow function: 64/65
• Serial input 14-bit programmable reference divider: R = 5 to 16,383
• Serial input 18-bit programmable divider consisting of:
- Binary 6-bit swallow counter: 0 to 63
- Binary 12-bit programmable counter: 5 to 4,095
• Wide operating temperature: Ta = –20 to 60°C
s
PACKAGES
16-pin, Plastic SSOP
20-pin, Plastic SSOP
(FPT-16P-M05)
(FPT-20P-M03)
1
MB15C02
s
PIN DESCRIPTIONS
Pin no.
SSOP SSOP
16
20
1
2
–
3
4
1
2
3
4
5
Pin
name
V
DD
Clock
NC
Data
LE
I/O
–
I
–
I
I
Power supply voltage
Clock input for the shift register.(Schmitt trigger input)
Data is shifted into the shift register on the rising edge of the clock.
No connection
Serial data input using binary code.(Schmitt
trigger input)
Load enable signal input
(Schmitt trigger input)
When LE is high, the data in the shift register is transferred to a latch,
according to the control bit in the serial data.
Prescaler input.
A bias circuit and amplifier are at input port. Connection with an external
VCO should be done by AC coupling.
Power saving mode control. This pin must be set at “L” at Power-ON.
PS = “H” ; Normal mode
PS = “L” ; Power saving mode
No connection
Lock detector signal output.
When a PLL is locking, LD outputs “H”.
When a PLL is not locking, LD outputs “L”.
Charge pump output.
Phase of the charge pump can be reversed by FC input. The Do output
may be inverted by FC input. The relationships between the programmable
reference divider output (fr) and the programmable divider output (fp) are
shown below;
fr > fp :“H” level (FC = “L”), “L” level (FC = “H”)
fr = fp : High impedance
fr < fp :“L” level (FC = “L”), “H” level (FC = “H”)
Power supply for the charge pump.
Phase comparator output pin (for external charge pump). Relation between
the programmable reference divider output (fr) and the programmable divider
output (fp) are shown below;
When FC = “L”
fr > fp :
φR
= “L” level,
φP
= “L” level
fr = fp :
φR
= “L” level,
φP
= High impedance
fr < fp :
φR
= “H” level,
φP
= High impedance
When FC = “H”
fr > fp :
φR
= “H” level,
φP
= High impedance
fr = fp :
φR
= “L” level,
φP
= High impedance
fr < fp :
φR
= “L” level,
φP
= “L” level
No connection
Phase comparator output pin (for external charge pump). Refer to Pin
description for
φR. φP
pin is a Nch open drain output.
Phase comparator input select pin.
Test mode select pin.
(Pull down resistor)
Please set this pin to ground or open usually.
Descriptions
5
6
fin
I
6
–
7
7
8
9
PS
NC
LD
I
–
O
8
10
Do
O
9
11
Vp
–
10
12
φR
O
–
11
12
13
13
14
15
16
NC
φP
FC
TEST
–
O
I
I
(Continued)
3
MB15C02
(Continued)
Pin no.
SSOP SSOP
16
20
14
–
15
16
17
18
19
20
Pin
name
OSC
OUT
NC
OSC
IN
V
SS
I/O
O
–
I
–
Descriptions
Oscillator output.
Connection for an external crystal.
No connection
Programmable reference divider input.
Oscillator input.
Clock can be input to OSC
IN
from outside. In the case, please leave OSC
OUT
pin open and make connection with OSC
IN
as AC coupling.
Ground pin.
4
京公网安备 11010802033920号
EEWORLD
