GS8180D18GD-100T datasheet, PDF

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GS8180D18GD-100T: DescriptionStandard SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; Categorystorage storage; File Size1MB，28 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8180D18GD-100T Overview

Standard SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8180D18GD-100T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.B
Maximum access time	3 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	15 mm
memory density	18874368 bit
Memory IC Type	STANDARD SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX18
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm
Base Number Matches	1

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GS8180D18D-250/200/167/133/100

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +150/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices

• Pb-Free 165-bump BGA package available

18Mb Burst of 4

SigmaQuad SRAM

250 MHz–100 MHz

1.8 V V

1.8 V or 1.5 V I/O

SigmaRAM™ Family Overview

GS8180D18 are built in compliance with the SigmaQuad

SRAM pinout standard for Separate I/O synchronous SRAMs.

They are 18,874,368-bit (18Mb) SRAMs. These are the first in

a family of wide, very low voltage HSTL I/O SRAMs designed

to operate at the speeds needed to implement economical high

performance networking systems.

for

-250

Parameter Synopsis

-200

5.0 ns

2.3 ns

-167

6.0 ns

2.5 ns

-133

7.5 ns

3.0 ns

-100

10 ns

3.0 ns

tKHKH

4.0 ns

tKHQV

2.1 ns

Rev: 2.04 4/2005

1/28

sig

n—

sco

inu

SigmaQuad SRAMs are offered in a number of configurations.

Some emulate and enhance other synchronous separate I/O

SRAMs. A higher performance SDR (Single Data Rate) Burst

of 2 version is also offered. The logical differences between

the protocols employed by these RAMs hinge mainly on

various combinations of address bursting, output data

registering, and write cueing. Along with the Common I/O

family of SigmaRAMs, the SigmaQuad family of SRAMs

allows a user to implement the interface protocol best suited to

the task at hand.

Clocking and Addressing Schemes

A Burst of 4 SigmaQuad SRAM is a synchronous device. It

employs two input register clock inputs, K and K. K and K are

independent single-ended clock inputs, not differential inputs

to a single differential clock input buffer. The device also

allows the user to manipulate the output register clock inputs

quasi independently with the C and C clock inputs. C and C are

also independent single-ended clock inputs, not differential

inputs. If the C clocks are tied high, the K clocks are routed

internally to fire the output registers instead.

Because Separate I/O Burst of 4 RAMs always transfer data in

four packets, A0 and A1 are internally set to 0 for the first read

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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