ADS1602
SBAS341B − DECEMBER 2004 − REVISED APRIL 2005
16-Bit, 2.5MSPS
Analog-to-Digital Converter
FEATURES
D
High Speed:
D
Data Rate: 2.5MSPS
Bandwidth: 1.23MHz
Outstanding Performance:
SNR: 91dB at f
IN
= 100kHz, −1dBFS
THD: −101dB at f
IN
= 100kHz, −6dBFS
SFDR: 103dB at f
IN
= 100kHz, −6dBFS
Ease-of-Use:
High-Speed 3-Wire Serial Interface
Directly Connects to TMS320 DSPs
On-Chip Digital Filter Simplifies Anti-Alias
Requirements
Simple Pin-Driven Control—No On-Chip
Registers to Program
Selectable On-Chip Voltage Reference
Simultaneous Sampling with Multiple
ADS1602s
Low Power:
530mW at 2.5MSPS
Power-Down Mode
DESCRIPTION
The ADS1602 is a high-speed, high-precision,
delta-sigma
analog-to-digital
converter
(ADC)
manufactured on an advanced CMOS process. The
ADS1602 oversampling topology reduces clock jitter
sensitivity during the sampling of high-frequency, large
amplitude signals by a factor of four over that achieved by
Nyquist-rate ADCs. Consequently, signal-to-noise ratio
(SNR) is particularly improved. Total harmonic distortion
(THD) is −101dB, and the spurious-free dynamic range
(SFDR) is 103dB.
Optimized for power and performance, the ADS1602
dissipates only 530mW while providing a full-scale
differential input range of
±3V.
Having such a wide input
range makes out-of-range signals unlikely. The OTR pin
indicates if an analog input out-of-range condition does
occur. The differential input signal is measured against the
differential reference, which can be generated internally or
supplied externally on the ADS1602.
The ADS1602 uses an inherently stable advanced
modulator with an on-chip decimation filter. The filter stop
band extends to 38.6MHz, which greatly simplifies the
anti-aliasing circuitry. The modulator samples the input
signal up to 40MSPS, depending on f
CLK
, while the 16x
decimation filter uses a series of four half-band FIR filter
stages to provide 75dB of stop band attenuation and
0.001dB of passband ripple.
Output data is provided over a simple 3-wire serial
interface at rates up to 2.5MSPS, with a −3dB bandwidth
of 1.23MHz. The output data or its complementary format
directly connects to DSPs such as TI’s TMS320 family,
FPGAs, or ASICs. A dedicated synchronization pin
enables simultaneous sampling with multiple ADS1602s
in multi-channel systems. Power dissipation is set by an
external resistor that allows a reduction in dissipation
when operating at slower speeds. All of the ADS1602
features are controlled by dedicated I/O pins, which
simplify operation by eliminating the need for on-chip
registers.
The high performing, easy-to-use ADS1602 is especially
suitable for demanding measurement applications in
sonar, vibration analysis, and data acquisition. The
ADS1602 is offered in a small, 7mm x 7mm TQFP-48
package and is specified from −40°C to +85°C.
D
D
APPLICATIONS
D
Sonar
D
Vibration Analysis
D
Data Acquisition
VREFP VREFN
VMID
RBIAS VCAP
AVDD
DVDD
IOVDD
CLK
SYNC
Reference and Bias Circuits
FSO
FSO
AINP
AINN
Serial
Interface
SCLK
SCLK
DOUT
DOUT
OTR
PD
∆Σ
Modulator
Linear Phase
FIR Digital Filter
ADS1602
AGND
DGND
REFEN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright
2004−2005, Texas Instruments Incorporated
www.ti.com
ADS1602
www.ti.com
SBAS341B − DECEMBER 2004 − REVISED APRIL 2005
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information see
the Package Option Addendum located at the end of this
datasheet or visit the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
ADS1602
AVDD to AGND
DVDD to DGND
IOVDD to DGND
AGND to DGND
Input Current
Input Current
Analog I/O to AGND
Digital I/O to DGND
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
−0.3 to +6
−0.3 to +3.6
−0.3 to +6
−0.3 to +0.3
100mA, Momentary
10mA, Continuous
−0.3 to AVDD + 0.3
−0.3 to IOVDD + 0.3
+150
−40 to +105
−60 to +150
V
V
°C
°C
°C
UNIT
V
V
V
V
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ADS1602 passes standard 200V machine model and 1.5K CDM
testing. ADS1602 passes 1kV human body model testing (TI Standard
is 2kV).
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Lead Temperature (soldering, 10s)
+260
°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
2
ADS1602
www.ti.com
SBAS341B − DECEMBER 2004 − REVISED APRIL 2005
ELECTRICAL CHARACTERISTICS
All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V,
and RBIAS = 37kΩ, unless otherwise noted.
ADS1602
PARAMETER
Analog Input
Differential input voltage (V
IN
)
(AINP − AINN)
Common-mode input voltage (V
CM
)
(AINP + AINN) / 2
Absolute input voltage
(AINP or AINN with respect to AGND)
Dynamic Specifications
Data Rate
f
IN
= 10kHz, −1dBFS
f
IN
= 10kHz, −3dBFS
f
IN
= 10kHz, −6dBFS
f
IN
= 100kHz, −1dBFS
Signal-to-noise ratio (SNR)
f
IN
= 100kHz, −3dBFS
f
IN
= 100kHz, −6dBFS
f
IN
= 800kHz, −1dBFS
f
IN
= 800kHz, −3dBFS
f
IN
= 800kHz, −6dBFS
f
IN
= 10kHz, −1dBFS
f
IN
= 10kHz, −3dBFS
f
IN
= 10kHz, −6dBFS
f
IN
= 100kHz, −1dBFS
Total harmonic distortion (THD)
f
IN
= 100kHz, −3dBFS
f
IN
= 100kHz, −6dBFS
f
IN
= 800kHz, −1dBFS
f
IN
= 800kHz, −3dBFS
f
IN
= 800kHz, −6dBFS
f
IN
= 10kHz, −1dBFS
f
IN
= 10kHz, −3dBFS
f
IN
= 10kHz, −6dBFS
f
IN
= 100kHz, −1dBFS
Signal-to-noise + distortion (SINAD)
f
IN
= 100kHz, −3dBFS
f
IN
= 100kHz, −6dBFS
f
IN
= 800kHz, −1dBFS
f
IN
= 800kHz, −3dBFS
f
IN
= 800kHz, −6dBFS
f
IN
= 10kHz, −1dBFS
f
IN
= 10kHz, −3dBFS
f
IN
= 10kHz, −6dBFS
f
IN
= 100kHz, −1dBFS
Spurious-free dynamic range (SFDR)
f
IN
= 100kHz, −3dBFS
f
IN
= 100kHz, −6dBFS
f
IN
= 800kHz, −1dBFS
f
IN
= 800kHz, −3dBFS
f
IN
= 800kHz, −6dBFS
Intermodulation distortion (IMD)
Aperture delay
f
1
= 995kHz, −6dBFS
f
2
= 1005kHz, −6dBFS
90
93
90
93
85
82
85
82
87
84
87
84
2.50
f
CLK
40MHz
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0dBFS
±V
REF
V
V
4.6
V
1.45
−0.1
MSPS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
−92
−93
dB
dB
dB
−90
−92
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ns
92
90
87
91
89
86
91
89
86
−94
−106
−108
−90
−96
−101
−116
−114
−110
89
90
87
87
88
86
91
89
86
95
107
112
91
96
103
120
119
114
94
4
3
ADS1602
www.ti.com
SBAS341B − DECEMBER 2004 − REVISED APRIL 2005
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V,
and RBIAS = 37kΩ, unless otherwise noted.
ADS1602
PARAMETER
Digital Filter Characteristics
Passband
Passband ripple
−0.1dB attenuation
Passband transition
−3.0dB attentuation
f
CLK
40MHz
1.23
f
CLK
40MHz
f
CLK
40MHz
1.15
f
CLK
40MHz
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
1.1
f
CLK
40MHz
MHz
dB
MHz
±0.001
MHz
Stop band
Stop band attenuation
Group delay
1.4
38.6
MHz
dB
75
10.4
40MHZ
f
CLK
40MHZ
f
CLK
µs
Settling time
Static Specifications
Resolution
No missing codes
Input-referred noise
Integral nonlinearity
Differential nonlinearity
Offset error
Offset error drift
Gain error
Gain error drift
Common-mode rejection
Power-supply rejection
Internal Voltage Reference
V
REF
= (VREFP − VREFN)
VREFP
VREFN
VMID
V
REF
drift
Startup time
External Voltage Reference
V
REF
= (VREFP − VREFN)
VREFP
VREFN
VMID
Complete settling
20.4
µs
16
16
0.5
−1dBFS signal
0.75
0.25
−0.1
−0.1
0.25
Excluding reference drift
At DC
At DC
REFEN = low
2.75
3.5
0.5
2.3
3
4.0
1.0
2.5
50
15
REFEN = high
2.0
3.5
0.5
2.3
3
4
1
2.5
3.25
4.25
1.5
2.6
3.25
4.3
1.3
2.7
10
75
65
0.85
Bits
Bits
LSB, rms
LSB
LSB
%FSR
ppmFSR/°C
%
ppm/°C
dB
dB
V
V
V
V
ppm/°C
ms
V
V
V
V
4
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