K4S643232C
Revision History
Revision 1.1 (November 17th, 1999)
• Corrected typo in ordering information on page 3
CMOS SDRAM
Revision 1.0 (October, 1999)
• Changed part number from KM432S2030CT-G/F to K4S643232C-TC/TL according to re-organized code system
-2-
REV. 1.1 Nov. '99
K4S643232C
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
•
•
•
•
3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
15.6us refresh duty cycle
CMOS SDRAM
GENERAL DESCRIPTION
The K4S643232C is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
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•
•
•
•
ORDERING INFORMATION
Part NO.
K4S643232C-TC/L55
K4S643232C-TC/L60
K4S643232C-TC/L70
K4S643232C-TC/L80
K4S643232C-TC/L10
Max Freq.
183MHz
166MHz
143MHz
125MHz
100MHz
Interface
Package
LVTTL
86
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select
512K x 32
512K x 32
512K x 32
512K x 32
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
-3-
REV. 1.1 Nov. '99
K4S643232C
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
CMOS SDRAM
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
10
, Column address : CA
0
~ CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No connection on the device.
CKE
Clock enable
A
0
~ A
10
BA0,1
RAS
CAS
WE
DQM0 ~ 3
DQ
0
~
31
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No Connection
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
CAPACITANCE
Clock
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
= 1.4V
±
200 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.5
2.5
2.5
4.0
Max
4
4.5
4.5
6.5
Unit
pF
pF
pF
pF
RAS, CAS, WE, CS, CKE, DQM
Address
DQ
0
~ DQ
31
-5-
REV. 1.1 Nov. '99
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