S29PL127J/S29PL129J/S29PL064J/S29PL032J
128/128/64/32 Megabit (8/8/4/2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory with Enhanced VersatileIO
TM
Control
PRELIMINARY
Distinctive Characteristics
ARCHITECTURAL ADVANTAGES
128/128/64/32 Mbit Page Mode devices
— Page size of 8 words: Fast page read access from
random locations within the page
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and
program operations for battery-powered applications
Dual Chip Enable inputs (only in PL129J)
— Two CE# inputs control selection of each half of the
memory space
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
FlexBank Architecture (PL127J/PL064J/PL032J)
— 4 separate banks, with up to two simultaneous
operations per device
— Bank A:
PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
— Bank B:
PL127J - 48 Mbit (32 Kw x 96)
PL064J - 24 Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
— Bank C:
PL127J - 48 Mbit (32 Kw x 96)
PL064J - 24 Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
— Bank D:
PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
FlexBank Architecture (PL129J)
— 4 separate banks, with up to two simultaneous
operations per device
— CE#1 controlled banks:
Bank 1A:
PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)
Bank 1B:
PL129J - 48Mbit (32Kw x 96)
— CE#2 controlled banks:
Bank 2A:
PL129J - 48 Mbit (32Kw x 96)
Bank 2B:
PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)
Enhanced VersatileI/O
TM
(V
IO
) Control
— Output voltage generated and input voltages
tolerated on all control inputs and I/Os is determined
by the voltage on the V
IO
pin
— V
IO
options at 1.8 V and 3 V I/O for PL127J and
PL129J devices
— 3V V
IO
for PL064J and PL032J devices
SecSi
TM
(Secured Silicon) Sector region
— Up to 128 words accessible through a command
sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110 nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector
typical
PERFORMANCE CHARACTERISTICS
High Performance
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 17 mA program/erase current
— 0.2 µA typical standby mode current
SOFTWARE FEATURES
Software command-set compatible with JEDEC
42.4 standard
— Backward compatible with Am29F, Am29LV,
Am29DL, and AM29PDL families and MBM29QM/RM,
MBM29LV, MBM29DL, MBM29PDL families
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or
program operations in other sectors of same bank
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
Publication Number
31107
Revision
A
Amendment
6
Issue Date
May 24, 2004
P R E L I M I N A R Y
HARDWARE FEATURES
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
WP#/ ACC (Write Protect/Acceleration) input
— At V
IL
, hardware level protection for the first and
last two 4K word sectors.
— At V
IH
, allows removal of sector protection
— At V
HH
, provides accelerated programming in a
factory setting
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector
— Sectors can be locked and unlocked in-system at V
CC
level
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
Package options
— Standard discrete pinouts
11 x 8 mm, 80-ball Fine-pitch BGA (PL127J/PL129J
(VBG080)
8.15 x 6.15 mm, 48-ball Fine pitch BGA
(PL064J/PL032J)
(VBK048)
— MCP-compatible pinout
8 x 11.6 mm, 64-ball Fine-pitch BGA (PL127J and
PL129J)
7 x 9 mm, 56-ball Fine-pitch BGA (PL064J and
PL032J)
Compatible with MCP pinout, allowing easy
integration of RAM into existing designs
— 20 x 14 mm, 56-pin TSOP (PL127J) (TS056)
2
S29PL127J/S29PL129J/S29PL064J/S29PL032J
31107A6 May 24, 2004
P R E L I M I N A R Y
General Description
The PL127J/PL129J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page
Mode and Simultaneous Read/Write Flash memory device organized as 8/8/4/2
Mwords. The devices are offered in the following packages:
11mm x 8mm, 80-ball Fine-pitch BGA standalone (PL127J and PL129J)
8mm x 11.6mm,
(PL127J/PL129J)
64-ball
Fine-pitch
BGA
multi-chip
compatible
8.15mm x 6.15mm, 48-ball Fine-pitch BGA standalone (PL064J/PL032J)
7mm x 9mm, 56-ball Fine-pitch BGA multi-chip compatible (PL064J and
PL032J)
20mm x 14mm, 56-pin TSOP (PL127J)
The word-wide data (x16) appears on DQ15-DQ0. This device can be pro-
grammed in-system or in standard EPROM programmers. A 12.0 V V
PP
is not
required for write or erase operations.
The device offers fast page access times of 20 to 30 ns, with corresponding ran-
dom access times of 55 to 70 ns, respectively, allowing high speed
microprocessors to operate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space into 4 banks, which can be considered to be four
separate memory arrays as far as certain operations are concerned. The device
can improve overall system performance by allowing a host system to program
or erase in one bank, then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations operating at any one
time). This releases the system from waiting for the completion of a program or
erase operation, greatly improving system performance.
The device can be organized in both top and bottom sector configurations. The
banks are organized as follows:
Bank
A
B
C
D
PL127J Sectors
16 Mbit (4 Kw x 8 and 32 Kw x 31)
48 Mbit (32 Kw x 96)
48 Mbit (32 Kw x 96)
16 Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J Sectors
8 Mbit (4 Kw x 8 and 32 Kw x 15)
24 Mbit (32 Kw x 48)
24 Mbit (32 Kw x 48)
8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J Sectors
4 Mbit (4 Kw x 8 and 32 Kw x 7)
12 Mbit (32 Kw x 24)
12 Mbit (32 Kw x 24)
4 Mbit (4 Kw x 8 and 32 Kw x 7)
Bank
1A
1B
2A
2B
PL129J Sectors
16 Mbit (4 Kw x 8 and 32 Kw x 31)
48 Mbit (32 Kw x 96)
48 Mbit (32 Kw x 96)
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE# Control
CE1#
CE1#
CE2#
CE2#
May 24, 2004 31107A6
S29PL127J/S29PL129J/S29PL064J/S29PL032J
3
P R E L I M I N A R Y
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode
operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a
single 3.0 volt power supply
(2.7 V to 3.6 V) for both
read and write functions. Internally generated and regulated voltages are pro-
vided for the program and erase operations.
The device is entirely command set compatible with the
JEDEC 42.4 sin-
gle-power-supply Flash standard.
Commands are written to the command
register using standard microprocessor write timing. Register contents serve as
inputs to an internal state-machine that controls the erase and programming cir-
cuitry. Write cycles also internally latch addresses and data needed for the
programming and erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. The
Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four. Device erasure occurs by executing
the erase command sequence.
The host system can detect whether a program or erase operation is complete by
reading the DQ7 (Data# Polling) and DQ6 (toggle)
status bits.
After a program
or erase cycle has been completed, the device is ready to read array data or ac-
cept another command.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume
feature enables the user to put erase on
hold for any period of time to read data from, or program data to, any sector that
is not selected for erasure. True background erase can thus be achieved. If a read
is needed from the SecSi Sector area (One Time Program area) after an erase
suspend, then the user must use the proper command sequence to enter and exit
this region.
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the
automatic sleep mode.
The system can also place the device into the standby mode. Power consumption
is greatly reduced in both these modes.
The device electrically erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
4
S29PL127J/S29PL129J/S29PL064J/S29PL032J
31107A6 May 24, 2004
P R E L I M I N A R Y
TABLE OF CONTENTS
Simultaneous Read/Write Operation with Zero Latency ........................3
Page Mode Features .............................................................................................4
Standard Flash Memory Features .....................................................................4
Persistent Sector Protection . . . . . . . . . . . . . . . . 50
Persistent Protection Bit (PPB) ......................................................................50
Persistent Protection Bit Lock (PPB Lock) .................................................50
Dynamic Protection Bit (DYB) .......................................................................50
Persistent Sector Protection Mode Locking Bit ....................................... 52
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . .5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .7
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 11
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Simultaneous Read/Write Block Diagram . . . . . 12
Simultaneous Read/Write Block Diagram (PL129J)
13
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 14
80-Ball Fine-pitch BGA ...................................................................................... 14
Special Package Handling Instructions ...................................................... 14
64-Ball Fine-pitch BGA—MCP Compatible .................................................15
Special Package Handling Instructions .......................................................15
48-Ball Fine-pitch BGA ...................................................................................... 16
Password Protection Mode . . . . . . . . . . . . . . . . . 52
Password and Password Mode Locking Bit ................................................ 52
64-bit Password .................................................................................................. 53
Write Protect (WP#) ....................................................................................... 53
Persistent Protection Bit Lock ................................................................... 53
High Voltage Sector Protection ..................................................................... 54
Figure 1. In-System Sector Protection/Sector Unprotection Algo-
rithms.............................................................................. 55
Temporary Sector Unprotect ........................................................................ 56
Figure 2. Temporary Sector Unprotect Operation ................... 56
Connection Diagram (PL064J and PL032J) . . . . . . 17
56-pin TSOP 20 x 14 mm Configuration (PL127J) ...................................... 18
Special Package Handling Instructions ...................................................... 18
SecSi™ (Secured Silicon) Sector Flash Memory Region .......................... 56
Factory-Locked Area (64 words) .............................................................. 56
Customer-Lockable Area (64 words) ...................................................... 57
SecSi Sector Protection Bits ....................................................................... 57
Figure 3. SecSi Sector Protect Verify .................................... 58
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .20
Table 1. PL127J Device Bus Operations ................................ 20
Table 2. PL129J Device Bus Operations ................................ 20
Hardware Data Protection .............................................................................58
Low VCC Write Inhibit ................................................................................ 58
Write Pulse “Glitch” Protection ............................................................... 58
Logical Inhibit ................................................................................................... 58
Power-Up Write Inhibit ............................................................................... 58
Requirements for Reading Array Data ......................................................... 21
Random Read (Non-Page Read) ................................................................ 21
Page Mode Read .............................................................................................. 21
Table 3. Page Select .......................................................... 21
Common Flash Memory Interface (CFI) . . . . . . 59
Table 17. CFI Query Identification String .............................. 59
Table 18. System Interface String ........................................ 60
Table 19. Device Geometry Definition ................................... 60
Table 20. Primary Vendor-Specific Extended Query ................ 61
Simultaneous Read/Write Operation .......................................................... 22
Table 4. Bank Select .......................................................... 22
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 63
Reading Array Data ........................................................................................... 63
Reset Command ................................................................................................. 63
Autoselect Command Sequence ....................................................................64
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ................64
Word Program Command Sequence ...........................................................64
Unlock Bypass Command Sequence ........................................................ 65
Figure 4. Program Operation ............................................... 66
Writing Commands/Command Sequences ................................................ 22
Accelerated Program Operation ...............................................................23
Autoselect Functions .....................................................................................23
Automatic Sleep Mode ......................................................................................23
RESET#: Hardware Reset Pin ........................................................................ 24
Output Disable Mode ....................................................................................... 24
Table 5. PL127J Sector Architecture ..................................... 25
Table 6. PL064J Sector Architecture ..................................... 32
Table 7. PL032J Sector Architecture ..................................... 35
Table 8. S29PL129J Sector Architecture ............................... 37
Table 9. SecSiTM Sector Addresses ...................................... 43
Chip Erase Command Sequence ................................................................... 66
Sector Erase Command Sequence ................................................................ 67
Figure 5. Erase Operation ................................................... 68
Autoselect Mode .................................................................................................43
Table 10. Autoselect Codes (High Voltage Method) ................ 44
Table 11. Autoselect Codes for PL129J ................................. 44
Table 12. PL127J Boot Sector/Sector Block Addresses for
Protection/Unprotection ..................................................... 45
Table 13. PL129J Boot Sector/Sector Block Addresses for
Protection/Unprotection ..................................................... 46
Table 14. PL064J Boot Sector/Sector Block Addresses for
Protection/Unprotection ..................................................... 47
Table 15. PL032J Boot Sector/Sector Block Addresses for
Protection/Unprotection ..................................................... 48
Erase Suspend/Erase Resume Commands ..................................................68
Command Definitions Tables .........................................................................70
Table 21. Memory Array Command Definitions ...................... 70
Table 22. Sector Protection Command Definitions .................. 72
Write Operation Status . . . . . . . . . . . . . . . . . . . . 73
DQ7: Data# Polling ............................................................................................ 73
Figure 6. Data# Polling Algorithm ........................................ 74
DQ6: Toggle Bit I ............................................................................................... 75
Figure 7. Toggle Bit Algorithm ............................................. 76
Selecting a Sector Protection Mode ............................................................. 48
Table 16. Sector Protection Schemes ................................... 49
DQ2: Toggle Bit II .............................................................................................. 76
Reading Toggle Bits DQ6/DQ2 ..................................................................... 76
DQ5: Exceeded Timing Limits ........................................................................ 77
DQ3: Sector Erase Timer ................................................................................ 77
Table 23. Write Operation Status ......................................... 78
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 49
Persistent Sector Protection .......................................................................... 49
Password Sector Protection ........................................................................... 49
WP# Hardware Protection ............................................................................ 49
Selecting a Sector Protection Mode ............................................................. 49
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 79
Figure 8. Maximum Overshoot Waveforms ............................ 79
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .80
Industrial (I) Devices ..........................................................................................80
May 24, 2004 31107A6
S29PL127J/S29PL129J/S29PL064J/S29PL032J
5
Microcontroller MCU
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