D5AC312-30 datasheet, PDF - EEWORLD Datasheet

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D5AC312-30: DescriptionUV PLD, 30ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24; CategoryProgrammable logic devices Programmable logic; File Size594KB，18 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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D5AC312-30 Overview

UV PLD, 30ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24

D5AC312-30 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	DIP
package instruction	DIP, DIP24,.3
Contacts	24
Reach Compliance Code	compliant
Other features	PAL WITH MACROCELLS; 12 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK
Architecture	PAL-TYPE
maximum clock frequency	23.8 MHz
JESD-30 code	R-GDIP-T24
JESD-609 code	e0
length	32.07 mm
Dedicated input times	8
Number of I/O lines	12
Number of entries	22
Output times	12
Number of product terms	200
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8 DEDICATED INPUTS, 12 I/O
Output function	MACROCELL
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	UV PLD
propagation delay	30 ns
Certification status	Not Qualified
Maximum seat height	5.72 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

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D5AC312-30 Related Products

	D5AC312-30	P5AC312-30	N5AC312-30	P5AC312-25	D5AC312-25
Description	UV PLD, 30ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24	OT PLD, 30ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24	OT PLD, 30ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28	OT PLD, 25ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24	UV PLD, 25ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Intel	Intel	Intel	Intel	Intel
Parts packaging code	DIP	DIP	QLCC	DIP	DIP
package instruction	DIP, DIP24,.3	DIP, DIP24,.3	QCCJ, LDCC28,.5SQ	DIP, DIP24,.3	DIP, DIP24,.3
Contacts	24	24	28	24	24
Reach Compliance Code	compliant	compliant	compliant	compliant	unknown
Other features	PAL WITH MACROCELLS; 12 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	PAL WITH MACROCELLS; 12 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	PAL WITH MACROCELLS; 12 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	PAL WITH MACROCELLS; 12 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	PAL WITH MACROCELLS; 12 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK
Architecture	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE
maximum clock frequency	23.8 MHz	23.8 MHz	23.8 MHz	28.5 MHz	28.5 MHz
JESD-30 code	R-GDIP-T24	R-PDIP-T24	S-PQCC-J28	R-PDIP-T24	R-GDIP-T24
JESD-609 code	e0	e0	e0	e0	e0
length	32.07 mm	31.61 mm	11.5062 mm	31.61 mm	32.07 mm
Dedicated input times	8	8	8	8	8
Number of I/O lines	12	12	12	12	12
Number of entries	22	22	22	22	22
Output times	12	12	12	12	12
Number of product terms	200	200	200	200	200
Number of terminals	24	24	28	24	24
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C
organize	8 DEDICATED INPUTS, 12 I/O	8 DEDICATED INPUTS, 12 I/O	8 DEDICATED INPUTS, 12 I/O	8 DEDICATED INPUTS, 12 I/O	8 DEDICATED INPUTS, 12 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED
encapsulated code	DIP	DIP	QCCJ	DIP	DIP
Encapsulate equivalent code	DIP24,.3	DIP24,.3	LDCC28,.5SQ	DIP24,.3	DIP24,.3
Package shape	RECTANGULAR	RECTANGULAR	SQUARE	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	CHIP CARRIER	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V	5 V	5 V	5 V
Programmable logic type	UV PLD	OT PLD	OT PLD	OT PLD	UV PLD
propagation delay	30 ns	30 ns	30 ns	25 ns	25 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.72 mm	4.32 mm	4.57 mm	4.32 mm	5.72 mm
Maximum supply voltage	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	YES	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	J BEND	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	1.27 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	QUAD	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	7.62 mm	7.62 mm	11.5062 mm	7.62 mm	7.62 mm
Base Number Matches	1	1	1	-	-

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