DAC1205D750HW datasheet, PDF - EEWORLD Datasheet

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DAC1205D750HW: DescriptionIC PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PQFP100, 14 X 14 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT638-1, HTQFP-100, Digital to Analog Converter; CategoryAnalog mixed-signal IC converter; File Size298KB，43 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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DAC1205D750HW Overview

IC PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PQFP100, 14 X 14 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT638-1, HTQFP-100, Digital to Analog Converter

DAC1205D750HW Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	QFP
package instruction	14 X 14 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT638-1, HTQFP-100
Contacts	100
Reach Compliance Code	unknown
Maximum analog output voltage	3.6 V
Minimum analog output voltage	1.8 V
Converter type	D/A CONVERTER
Enter bit code	OFFSET BINARY, 2\'S COMPLEMENT BINARY
Input format	PARALLEL, WORD
JESD-30 code	S-PQFP-G100
length	14 mm
Number of digits	12
Number of functions	1
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	HTFQFP
Package shape	SQUARE
Package form	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.2 mm
Nominal settling time (tstl)	0.02 µs
Nominal supply voltage	1.8 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	14 mm
Base Number Matches	1

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DAC1205D750

Dual 12-bit DAC, up to 750 Msps; 4x and 8x interpolating

Rev. 4 — 31 January 2012

Product data sheet

1. General description

The DAC1205D750 is a high-speed 12-bit dual channel Digital-to-Analog Converter

(DAC) with selectable 4 or 8 interpolating filters optimized for multi-carrier wireless

transmitters.

Thanks to its digital on-chip modulation, the DAC1205D750 allows the complex I and Q

inputs to be converted from BaseBand (BB) to IF. The mixing frequency is adjusted via a

Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and

the phase is controlled by a 16-bit register.

Two modes of operation are available: separate data ports or a single interleaved

high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into

its original I and Q data and then latched.

A 4 and 8 clock multiplier enables the DAC1205D750 to provide the appropriate

internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use

of an external high frequency clock. The voltage regulator enables adjustment of the

output full-scale current.

2. Features and benefits



Dual 12-bit resolution



IMD3: 74 dBc; f

= 737.28 Msps;

= 140 MHz

750 Msps maximum update rate



ACPR: 69 dBc; 2-carrier WCDMA;

= 737.28 Msps; f

= 153.6 MHz

Selectable 4 or 8 interpolation filters



Typical 1.2 W power dissipation at 4

interpolation, PLL off and 740 Msps

Input data rate up to 185 Msps



Power-down and Sleep modes

Very low noise cap-free integrated PLL



Differential scalable output current from

1.6 mA to 22 mA

32-bit programmable NCO frequency



On-chip 1.29 V reference

Dual port or Interleaved data modes



External analog offset control

(10-bit auxiliary DACs)

1.8 V and 3.3 V power supplies



Internal digital offset control

LVDS compatible clock



Inverse x / (sin x) function

Two’s complement or binary offset



Fully compatible SPI port

data format

1.8 V/3.3 V CMOS input data buffers



Industrial temperature range from

40 C

to +85

C

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