HD74LV1GT00AVSE-E datasheet, PDF

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HD74LV1GT00AVSE-E: DescriptionLV/LV-A/LVX/H SERIES, 2-INPUT NAND GATE, PDSO5, 1.20 X 1.60 MM, 0.50 MM PITCH, PLASTIC, VSON-5; Categorylogic logic; File Size101KB，7 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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HD74LV1GT00AVSE-E Overview

LV/LV-A/LVX/H SERIES, 2-INPUT NAND GATE, PDSO5, 1.20 X 1.60 MM, 0.50 MM PITCH, PLASTIC, VSON-5

HD74LV1GT00AVSE-E Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
Parts packaging code	SON
package instruction	VSOF,
Contacts	5
Reach Compliance Code	compliant
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-F5
length	1.6 mm
Logic integrated circuit type	NAND GATE
Humidity sensitivity level	1
Number of functions	1
Number of entries	2
Number of terminals	5
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	VSOF
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	14 ns
Certification status	Not Qualified
Maximum seat height	0.6 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	FLAT
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	1.2 mm
Base Number Matches	1

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HD74LV1GT00A

2–input NAND Gate / CMOS Logic Level Shifter

REJ03D0115-0900

Rev.9.00

Mar 21, 2008

Description

The HD74LV1GT00A is high-speed CMOS two input NAND gate using silicon gate CMOS process. With CMOS low

power dissipation, it provides high-speed equivalent to LS–TTL series. The internal circuit of three stages construction

with buffer provides wide noise margin and stable output. The input protection circuitry on this device allows over

voltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0

V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply.

Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the

low power consumption extends the battery life.

Features

•

The basic gate function is lined up as Renesas uni logic series.

•

Supplied on emboss taping for high-speed automatic mounting.

•

TTL compatible input level.

Supply voltage range : 3.0 to 5.5 V

Operating temperature range : –40 to +85°C

•

Logic-level translate function

3.0 V CMOS logic

→

5.0 V CMOS logic (@V

= 5.0 V)

1.8 V or 2.5 V CMOS logic

→

3.3 V CMOS logic (@V

= 3.3 V)

•

All inputs V

(Max.) = 5.5 V (@V

= 0 V to 5.5 V)

All outputs V

(Max.) = 5.5 V (@V

= 0 V)

•

Output current ±6 mA (@V

= 3.0 V to 3.6 V), ±12 mA (@V

= 4.5 V to 5.5 V)

•

All the logical input has hysteresis voltage for the slow transition.

•

Ordering Information

Part Name

HD74LV1GT00ACME

HD74LV1GT00AVSE

Note:

Package Type

CMPAK–5 pin

VSON–5 pin

Package Code

(Previous Code)

PTSP0005ZC-A

(CMPAK-5V)

PUSN0005KA-A

(TNP-5DV)

Package

Abbreviation

Taping Abbreviation

(Quantity)

E (3000 pcs/reel)

Please consult the sales office for the above package availability.

REJ03D0115-0900 Rev.9.00, Mar 21, 2008

Page 1 of 6

HD74LV1GT00AVSE-E Related Products

	HD74LV1GT00AVSE-E	HD74LV1GT00ACME-E
Description	LV/LV-A/LVX/H SERIES, 2-INPUT NAND GATE, PDSO5, 1.20 X 1.60 MM, 0.50 MM PITCH, PLASTIC, VSON-5	LV/LV-A/LVX/H SERIES, 2-INPUT NAND GATE, PDSO5, SC-88A, CMPAK-5
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	SON	SOIC
package instruction	VSOF,	TSSOP,
Contacts	5	5
Reach Compliance Code	compliant	compliant
series	LV/LV-A/LVX/H	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-F5	R-PDSO-G5
length	1.6 mm	2 mm
Logic integrated circuit type	NAND GATE	NAND GATE
Humidity sensitivity level	1	1
Number of functions	1	1
Number of entries	2	2
Number of terminals	5	5
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VSOF	TSSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260
propagation delay (tpd)	14 ns	14 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	0.6 mm	1.1 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	FLAT	GULL WING
Terminal pitch	0.5 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	20	20
width	1.2 mm	1.25 mm
Base Number Matches	1	1

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