MT58L32L32PT-10 datasheet, PDF

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MT58L32L32PT-10: DescriptionCache SRAM, 32KX32, 5ns, CMOS, PQFP100, PLASTIC, TQFP-100; Categorystorage storage; File Size364KB，18 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT58L32L32PT-10 Overview

Cache SRAM, 32KX32, 5ns, CMOS, PQFP100, PLASTIC, TQFP-100

MT58L32L32PT-10 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	PLASTIC, TQFP-100
Contacts	100
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.B
Maximum access time	5 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	1048576 bit
Memory IC Type	CACHE SRAM
memory width	32
Number of functions	1
Number of terminals	100
word count	32768 words
character code	32000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.01 A
Minimum standby current	3.14 V
Maximum slew rate	0.225 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm
Base Number Matches	1

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1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, SCD SYNCBURST SRAM

1Mb SYNCBURST

™

SRAM

FEATURES

• Fast clock and OE# access times

• Single +3.3V +0.3V/-0.165V power supply (V

)

• Separate +3.3V +0.3V/-0.165V isolated output

buffer supply (V

• SNOOZE MODE for reduced-power standby

• Single-cycle deselect (Pentium

BSRAM-

compatible)

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL

WRITE

• Three chip enables for simple depth expansion and

address pipelining

• Clock-controlled and registered addresses, data

I/Os and control signals

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down for portable applications

• 100-lead TQFP for high density, high speed

• Low capacitive bus loading

• x18, x32 and x36 options available

MT58L64L18P, MT58L32L32P,

MT58L32L36P

3.3V V

, 3.3V I/O, Pipelined, Single-

Cycle Deselect

100-Pin TQFP*

*JEDEC-standard MS-026 BHA (LQFP).

OPTIONS

• Timing (Access/Cycle/MHz)

3.5ns/6.0ns/166 MHz

4.2ns/7.5ns/133 MHz

5ns/10ns/100 MHz

• Configurations

64K x 18

32K x 32

32K x 36

• Package

100-pin TQFP

• Operating Temperature Range

Commercial (0ºC to +70ºC)

Part Number Example:

MARKING

-6

-7.5

-10

MT58L64L18P

MT58L32L32P

MT58L32L36P

None

MT58L64L18PT-10 IT

GENERAL DESCRIPTION

The Micron

SyncBurst

™

SRAM family employs

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

The MT58L64L18P and MT58L32L32/36P 1Mb

SRAMs integrate a 64K x 18, 32K x 32, or 32K x 36 SRAM

core with advanced synchronous peripheral circuitry

and a 2-bit burst counter. All synchronous inputs pass

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, SCD SyncBurst SRAM

MT58L64L18P.p65 – Rev. 9/99

through registers controlled by a positive-edge-trig-

gered single clock input (CLK). The synchronous inputs

include all addresses, all data inputs, active LOW chip

enable (CE#), two additional chip enables for easy

depth expansion (CE2, CE2#), burst control inputs

(ADSC#, ADSP#, ADV#), byte write enables (BWx#) and

global write (GW#).

Asynchronous inputs include the output enable

(OE#), clock (CLK) and snooze enable (ZZ). There is also

a burst mode pin (MODE) that selects between inter-

leaved and linear burst modes. The data-out (Q), en-

abled by OE#, is also asynchronous. WRITE cycles can

be from one to two bytes wide (x18) or from one to four

bytes wide (x32/x36), as controlled by the write control

inputs.

Burst operation can be initiated with either address

status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance

pin (ADV#).

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE

cycles. Individual byte enables allow individual bytes

to be written. During WRITE cycles on the x18 device,

BWa# controls DQa pins and DQPa; BWb# controls

DQb pins and DQPb. During WRITE cycles on the x32

and x36 devices, BWa# controls DQa pins and DQPa;

BWb# controls DQb pins and DQPb; BWc# controls

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT58L32L32PT-10 Related Products

	MT58L32L32PT-10	MT58L32L36PT-6	MT58L32L32PT-6	MT58L64L18PT-10	MT58L64L18PT-6
Description	Cache SRAM, 32KX32, 5ns, CMOS, PQFP100, PLASTIC, TQFP-100	Cache SRAM, 32KX36, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100	Cache SRAM, 32KX32, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100	Cache SRAM, 64KX18, 5ns, CMOS, PQFP100, PLASTIC, TQFP-100	Cache SRAM, 64KX18, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	QFP	QFP	QFP	QFP	QFP
package instruction	PLASTIC, TQFP-100	PLASTIC, TQFP-100	PLASTIC, TQFP-100	PLASTIC, TQFP-100	PLASTIC, TQFP-100
Contacts	100	100	100	100	100
Reach Compliance Code	not_compliant	unknown	not_compliant	unknown	not_compliant
ECCN code	3A991.B.2.B	3A991.B.2.A	3A991.B.2.B	3A991.B.2.A	3A991.B.2.A
Maximum access time	5 ns	3.5 ns	3.5 ns	5 ns	3.5 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	100 MHz	166 MHz	166 MHz	100 MHz	166 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609 code	e0	e0	e0	e0	e0
length	20 mm	20 mm	20 mm	20 mm	20 mm
memory density	1048576 bit	1179648 bit	1048576 bit	1179648 bit	1179648 bit
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
memory width	32	36	32	18	18
Number of functions	1	1	1	1	1
Number of terminals	100	100	100	100	100
word count	32768 words	32768 words	32768 words	65536 words	65536 words
character code	32000	32000	32000	64000	64000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C
organize	32KX32	32KX36	32KX32	64KX18	64KX18
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP	LQFP	LQFP	LQFP
Encapsulate equivalent code	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum standby current	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	0.225 mA	0.34 mA	0.34 mA	0.225 mA	0.34 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
width	14 mm	14 mm	14 mm	14 mm	14 mm
Base Number Matches	1	1	1	-	-
Maker	-	Micron Technology	-	Micron Technology	Micron Technology

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