1M x 4-Bit Dynamic RAM
(Hyper Page Mode (EDO) version)
HYB 314405BJ/BJL-50/-60/-70
Advanced Information
•
•
•
•
1 048 576 words by 4-bit organization
0 to 70 ˚C operating temperature
Hyper Page Mode - EDO
Performance:
-50
-60
60
15
30
104
25
-70
70
20
35
124
30
ns
ns
ns
ns
ns
t
RAC
t
CAC
t
AA
t
RC
t
HPC
RAS access time
CAS access time
Access time from address
Read/Write cycle time
Hyper page mode (EDO)
cycle time
50
13
25
89
20
•
•
Single + 3.3 V (± 0.3 V) supply
Low power dissipation
max. 252 mW active (-50 version)
max. 216 mW active (-60 version)
max. 198 mW active (-70 version)
Standby power dissipation:
7.2 mW max. standby (LVTTL)
3.6 mW max. standby (LVCMOS)
720
µW
max. standby (LVCMOS) for Low Power Version
Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh,
hidden refresh and test mode capability
All inputs and outputs LVTTL compatible
1024 refresh cycles / 16 ms
1024 refresh cycles / 128 ms for Low Power Version
Plastic Packages: P-SOJ-26/20-5 with 300 mil width
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Semiconductor Group
1
4.96
HYB 314405BJ/BJL-50/-60/-70
3.3V 1M x 4 EDO - DRAM
The HYB 314405BJ/BJL is the new generation dynamic RAM organized as 1 048 576 words by
4-bit. The HYB 314405BJ/BJL utilizes CMOS silicon gate process as well as advances circuit
techniques to provide wide operation margins, both internally and for the system user. Multiplexed
address inputs permit the HYB 314405BJ/BJL to be packed in a standard plastic P-SOJ-26/20
package. This package size provides high system bit densities and is compatible with commonly
used automatic testing and insertion equipment. System oriented features include single + 3.3 V
(± 0.3 V) power supply, direct interfacing with high performance logic device families.
Ordering Information
Type
HYB 314405BJ-50
HYB 314405BJ-60
HYB 314405BJ-70
HYB 314405BJL-50
HYB 314405BJL-60
HYB 314405BJL-70
Ordering Code
Q67100-Q2122
Q67100-Q2124
Q67100-Q2126
on request
on request
on request
Package
P-SOJ-26/20-5
P-SOJ-26/20-5
P-SOJ-26/20-5
P-SOJ-26/20-5
P-SOJ-26/20-5
P-SOJ-26/20-5
Descriptions
3.3 V EDO-DRAM
(access time 50 ns)
3.3 V EDO-DRAM
(access time 60 ns)
3.3 V EDO-DRAM
(access time 70 ns)
3.3 V Low Power EDO-DRAM
(access time 50 ns)
3.3 V Low Power EDO-DRAM
(access time 60 ns)
3.3 V Low Power EDO-DRAM
(access time 70 ns)
Semiconductor Group
2
HYB 314405BJ/BJL-50/-60/-70
3.3V 1M x 4 EDO - DRAM
Pin Configuration
(top view)
P-SOJ-26/20-5
Pin Names
A0-A9
RAS
CAS
WE
OE
I/O1 - I/O4
Address Input
Row Address Strobe
Column Address Strobe
Read/Write Input
Output Enable
Data Input/Output
Power Supply (+ 3.3 V)
Ground (0 V)
No Connection
V
CC
V
SS
N.C.
Semiconductor Group
3
HYB 314405BJ/BJL-50/-60/-70
3.3V 1M x 4 EDO - DRAM
Block Diagram
Semiconductor Group
4
HYB 314405BJ/BJL-50/-60/-70
3.3V 1M x 4 EDO - DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 ˚C
Storage temperature range......................................................................................– 55 to + 150 ˚C
Input/output voltage ..................................................................................................... – 1 to + 4.6 V
Power Supply voltage .................................................................................................. – 1 to + 4.6 V
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
T
A
= 0 to 70 ˚C,
V
SS
= 0 V,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 2 ns
Parameter
Input high voltage
Input low voltage
TTL Output high voltage (
I
OUT
= – 2 mA)
TTL Output low voltage (
I
OUT
= 2 mA)
CMOS Output high voltage (
I
OUT
= – 100
µA)
CMOS Output low voltage (
I
OUT
= 100
µA)
Input leakage current, any input
(0 V <
V
in
<
V
CC
+ 0.3 V, all other input = 0 V)
Output leakage current, any input
(DO is disabled, 0 V <
V
OUT
<
V
CC
+ 0.3 V)
Average
V
CC
supply current
-50 version
-60 version
-70 version
Standby
V
CC
supply current
(RAS = CAS = WE =
V
IH)
Average
V
CC
supply current during RAS-only
refresh cycles
-50 version
-60 version
-70 version
Average
V
CC
supply current during hyper page
mode (EDO) operation
-50 version
-60 version
-70 version
Symbol
Limit Values
min.
max.
0.8
–
0.4
0.2
10
10
2.0
– 1.0
2.4
–
–
– 10
– 10
Unit Test
Condition
1)
1)
1)
1)
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
I
I(L)
I
I(L)
I
CC1
V
CC
+ 0.5 V
V
V
V
V
V
µA
µA
mA
V
CC
– 0.2 –
1)
2) 3)4)
–
–
–
70
60
55
2
mA
mA
–
2)4)
I
CC2
I
CC3
–
–
–
–
70
60
55
mA
2) 3)4)
I
CC4
–
–
–
70
60
55
Semiconductor Group
5
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