• Function, pinout and drive compatible with FCT, F, and
AM29841 logic
• FCT-C speed at 5.5ns max. (Com’l)
FCT-B speed at 6.5ns max. (Com’l)
• Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
•
Matched rise and fall times
•
ESD > 2000V
• Fully compatible with TTL input and output logic levels
•
Sink current
64 mA (Com’l),
32 mA (Mil)
Source current 32 mA (Com’l),
12 mA (Mil)
•
High-speed parallel latches
•
Buffered common latch enable input
Functional Description
The FCT841T bus interface latch is designed to eliminate the
extra packages required to buffer existing latches and provide
extra data width for wider address/data paths or buses
carrying parity. The FCT841T is a buffered 10-bit wide version
of the FCT373 function.
The FCT841T high-performance interface is designed for
high-capacitance load drive capability while providing
low-capacitance bus loading at both inputs and outputs.
Outputs are designed for low-capacitance bus loading in the
high impedance state and are designed with a power-off
disable feature to allow for live insertion of boards.
Functional Block Diagram
D
0
D
1
D
2
D
3
D
4
D
5
D
N- 1
D
N
D
LE
Q
D
LE
Q
Q
D
LE
Q
Q
D
LE
Q
Q
D
LE
Q
Q
D
LE
Q
Q
D
LE
Q
Q
D
LE
Q
Q
LE
OE
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
N- 1
Y
N
Logic Block Diagram
D
10
D
LE
LE
OE
Q
10
Pin Configurations
DIP/QSOP/SOIC
Top View
Y
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
LE
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
September 1994 – Revised March 17, 1997
CY54/74FCT841T
Pin Description
Name
D
LE
Y
OE
I
I
O
I
I/O
The latch data inputs.
The latch enable input. The latches are transparent when LE is HIGH. Input data is latched on the
HIGH-to-LOW transition.
The three-state latch outputs.
The output enable control. When the OE is LOW, the outputs are enabled. When OE is HIGH, the outputs
Y
1
are in the high impedance (off) state.
Description
Function Table
[1]
Inputs
OE
H
H
H
H
L
L
L
LE
X
H
H
L
H
H
L
D
X
L
H
X
L
H
X
Internal Outputs
O
X
L
H
NC
L
H
NC
Y
Z
Z
Z
Z
L
H
NC
Function
High Z
Latched (High Z)
Transparent
Latched
Maximum Ratings
[2, 3]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –65°C to +135°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
DC Output Voltage ......................................... –0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ...... 120 mA
Power Dissipation.......................................................... 0.5W
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Operating Range
Range
Commercial
Military
[4]
Range
All
All
Ambient
Temperature
–40°C to +85°C
–55°C to +125°C
V
CC
5V
±
5%
5V
±
10%
Notes:
1. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, NC = No Change, Z = High Impedance.
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
4. T
A
is the “instant on” case temperature.
2
CY54/74FCT841T
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
Description
Output HIGH Voltage
Test Conditions
V
CC
= Min., I
OH
=
−32
mA
V
CC
= Min., I
OH
=
−15
mA
V
CC
= Min., I
OH
=
−12
mA
V
OL
V
IH
V
IL
V
H
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
OFF
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Hysteresis
[6]
Input Clamp Diode Voltage
Input HIGH Current
Input HIGH Current
Input LOW Current
Off State HIGH-Level Output
Current
Off State LOW-Level
Output Current
Output Short Circuit Current
[7]
Power-Off Disable
All inputs
V
CC
= Min., I
IN
=
−18
mA
V
CC
= Max., V
IN
= V
CC
V
CC
= Max., V
IN
= 2.7V
V
CC
= Max., V
IN
= 0.5V
V
CC
= Max., V
OUT
= 2.7V
V
CC
= Max., V
OUT
= 0.5V
V
CC
= Max., V
OUT
= 0.0V
V
CC
= 0V, V
OUT
= 4.5V
−60
−120
0.2
−0.7
−1.2
5
±1
±1
10
−10
−225
±1
V
CC
= Min., I
OL
= 64 mA
V
CC
= Min., I
OL
= 32 mA
Com’l
Com’l
Mil
Com’l
Mil
2.0
0.8
Min.
2.0
2.4
2.4
3.3
3.3
0.3
0.3
0.55
0.55
Typ.
[5]
Max.
Unit
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
mA
µA
Capacitance
[6]
Parameter
C
IN
C
OUT
Input Capacitance
Output Capacitance
Description
Typ.
[5]
5
9
Max.
10
12
Unit
pF
pF
Notes:
5. Typical values are at V
CC
=5.0V, T
A
=+25°C ambient.
6. This parameter is guaranteed but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
3
CY54/74FCT841T
Power Supply Characteristics
Parameter
I
CC
∆I
CC
I
CCD
Description
Test Conditions
Typ.
[5]
0.1
0.5
0.06
Max.
0.2
2.0
0.12
Unit
mA
mA
mA/MHz
Quiescent Power Supply Current V
CC
= Max., V
IN
≤
0.2V, V
IN
≥
V
CC
-0.2V
Quiescent Power Supply Current V
CC
= Max., V
IN
= 3.4V, f
1
= 0, Outputs Open
[8]
(TTL inputs HIGH)
Dynamic Power Supply Current
[9]
V
CC
= Max., 50% Duty Cycle, Outputs Open,
One Input Toggling, OE =GND, LE = V
CC
,
V
IN
≤
0.2V or V
IN
≥
V
CC
−0.2V
Total Power Supply Current
[10]
V
CC
=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f
1
=10 MHz,
OE = GND, LE = V
CC
,
V
IN
≤
0.2V or V
IN
≥
V
CC
−0.2V
V
CC
= Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f
1
=10 MHz,
OE = GND, LE = V
CC
,
V
IN
= 3.4V or V
IN
= GND
V
CC
= Max., 50% Duty Cycle, Outputs Open,
Ten Bits Toggling at f
1
= 2.5 MHz,
OE =GND, LE = V
CC
,
V
IN
≤
0.2V or V
IN
≥
V
CC
−0.2V
V
CC
=Max., 50% Duty Cycle, Outputs Open,
Ten Bits Toggling at f
1
= 2.5 MHz,
OE = GND, LE = V
CC
,
V
IN
= 3.4V or V
IN
= GND
Notes:
8. Per TTL driven input (V
IN
=3.4V); all other inputs at V
CC
or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+∆I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
= Quiescent Current with CMOS input levels
∆I
CC
= Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
f
1
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
I
C
0.7
1.4
mA
1.0
2.4
mA
1.0
3.2
[11]
mA
4.1
13.2
[11]
mA
4
CY54/74FCT841T
Switching Characteristics
Over the Operating Range
[12]
FCT841AT
Military
Parameter
t
PLH
t
PHL
Description
Propagation Delay
D
1
to Y
1
(L =HIGH)
Propagation Delay
D
1
to Y
1
(LE=HIGH)
t
SU
t
H
t
PLH
t
PHL
Data to LE Set-Up
Time
Data to LE Hold Time
Propagation Delay
LE to Y
1
Propagation Delay
LE to Y
1 [12]
t
W
t
PZH
t
PZL
Test Load
C
L
= 50 pF
R
L
= 500Ω
C
L
= 300 pF
R
L
= 500Ω
C
L
= 50 pF
R
L
= 500Ω
C
L
= 50 pF
R
L
= 500Ω
C
L
= 50 pF
R
L
= 500Ω
C
L
= 300 pF
R
L
= 500Ω
Min.
1.5
1.5
2.5
3.0
1.5
1.5
5.0
1.5
1.5
1.5
1.5
13.0
25.0
9.0
10.0
13.0
20.0
Max.
10.0
15.0
Commercial
Min.
1.5
1.5
2.5
2.5
1.5
1.5
4.0
1.5
1.5
1.5
1.5
11.5
23.0
7.0
8.0
12.0
16.0
Max.
9.0
13.0
FCT841BT
Commercial
Min.
1.5
1.5
2.5
2.5
1.5
1.5
4.0
1.5
1.5
1.5
1.5
8.0
14.0
6.0
7.0
8.0
15.5
Max.
6.5
13.0
FCT841CT
Commercial
Min.
1.5
1.5
2.5
2.5
1.5
1.5
4.0
1.5
1.5
1.5
1.5
6.5
12.0
5.7
6.0
6.4
15.0
5.5
13.0
Fig.
Max. Unit No.
[13]
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 3
1, 3
9
9
1, 3
1, 3
5
1, 7, 8
1, 7, 8
1, 7, 8
1, 7, 8
LE Pulse Width (HIGH) C
L
= 50 pF
R
L
= 500Ω
Output Enable Time
OE to Y
1
Output Enable Time
OE to Y
1[12]
C
L
= 50 pF
R
L
= 500Ω
C
L
= 300 pF
R
L
= 500Ω
C
L
= 5 pF
R
L
= 500Ω
C
L
= 50 pF
R
L
= 500Ω
t
PHZ
t
PLZ
Output Disable Time
OE to Y
1[12]
Output Disable Time
OE to Y
1
Ordering Information
Speed
(ns)
5.5
6.5
9.0
10.0
Ordering Code
CY74FCT841CTQC
CY74FCT841CTSOC
CY74FCT841BTQC
CY74FCT841BTSOC
CY74FCT841ATQC
CY74FCT841ATSOC
CY54FCT841ATDMB
Package
Name
Q13
S13
Q13
S13
Q13
S13
D14
Package Type
24-Lead (150-Mil) QSOP
24-Lead (300-Mil) Molded SOIC
24-Lead (150-Mil) QSOP
24-Lead (300-Mil) Molded SOIC
24-Lead (150-Mil) QSOP
24-Lead (300-Mil) Molded SOIC
24-Lead (300-Mil) CerDIP
Military
Commercial
Commercial
Operating
Range
Commercial
Notes:
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
京公网安备 11010802033920号
EEWORLD
