T4240
QorIQ Integrated Multicore
Communications Processor
Datasheet DS1146
FEATURES
•
12 e6500 cores built on Power Architecture
®
technology and
arranged as clusters of four e6500 cores sharing a 2 MB L2
cache
•
1.5 MB CoreNet platform cache (CPC)
•
Hierarchical interconnect fabric
– CoreNet fabric supporting coherent and non‐coherent
transactions with prioritization and bandwidth allocation
amongst CoreNet end‐points
– 1.6 Tbps coherent read bandwidth
•
Three 64‐bit DDR3 SDRAM memory controllers
– DDR3 and DDR3L with ECC and interleaving support
•
Data Path Acceleration Architecture (DPAA) incorporating
acceleration for the following functions:
– Packet parsing, classification, and distribution (Frame
Manager 1.1)
– Queue management for scheduling, packet sequencing,
and congestion management (Queue Manager 1.1)
– Hardware buffer management for buffer allocation and
de‐allocation (Buffer Manager 1.1)
– Cryptography Acceleration (SEC 5.0)
– RegEx Pattern Matching Acceleration (PME 2.0)
– Decompression/Compression Acceleration (DCE 1.0)
– DPAA chip‐to‐chip interconnect via RapidIO
Message Manager (RMan 1.0)
•
32 SerDes lanes at up to 10 GHz
•
Ethernet interfaces
– Up to four 10 Gbps Ethernet MACs
– Up to sixteen 1 Gbps Ethernet MACs
– Combinations of 1 Gbps and 10 Gbps Ethernet MACs
– IEEE Std 1588
™
support
•
High‐speed peripheral interfaces
– Four PCI Express 2.0/3.0 controllers running at up to 8
Gbps with one controllers supporting end‐point,
single‐root I/O virtualization (SR‐IOV)
– Two Serial RapidIO 2.0 controllers running at up to 5
Gbps
– Interlaken look‐aside interface for TCAM connection
•
Additional peripheral interfaces
– Two Serial ATA (SATA 2.0) controllers
– Two high‐speed USB 2.0 controllers with integrated
PHY
– Enhanced secure digital host controller (SD/MMC/
eMMC)
– Enhanced Serial peripheral interface (eSPI)
– Four I2C controllers
– Four 2‐pin UARTs or two 4‐pin DUARTs
– Integrated flash controller supporting NAND and NOR
flash
•
Three 8‐channel DMA engines
•
1932 FC‐PBGA package, 45 mm × 45 mm, 1mm pitch
Whilst Teledyne e2v Semiconductors SAS has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the
consequences of any use thereof and also reserves the right to change the specification of goods without notice. Teledyne e2v Semiconductors SAS accepts no
liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of the devices in accordance with
information contained herein.
Teledyne e2v Semiconductors SAS, avenue de Rochepleine 38120 Saint-Egrève, France
Telephone: +33 (0)4 76 58 30 00
Contact Teledyne e2v by e-mail: hotline-std@teledyne-e2v.com or visit www.teledyne-e2v.com for global sales and operations centres
Holding Company: Teledyne e2v Semiconductors SAS
Teledyne e2v Semiconductors SAS 2018
1146D–HIREL–10/18
T4240
1.
OVERVIEW
The T4240 QorIQ integrated multicore communications processor combines 12 dual‐threaded cores
built on Power Architecture
®
technology with high‐performance data path acceleration and network
and peripheral bus interfaces required for networking, telecom/ datacom, wireless infrastructure, and
military/aerospace applications.
This chip can be used for combined control, data path, and application layer processing in routers,
switches, gateways, and general‐purpose embedded computing systems. Its high level of integration
offers significant performance benefits compared to multiple discrete devices, while also simplifying
board design.
This figure shows the block diagram of the chip.
Figure 1‐1.
Block diagram
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
512 KB
Plat Cache
512 KB
Plat Cache
64-bit DDR3/3L
with ECC
64-bit DDR3/3L
with ECC
64-bit DDR3/3L
with ECC
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
2 MB Banked L2
512 KB
Plat Cache
MPIC
PreBoot Loader
Security Monitor
Internal BootROM
Power mgmt
SD/MMC
eSPI
4 x UART
4x I
2
C
IFC
2 x USB2.0 w/PHY
Clocks/Reset
GPIO
CCSR
DCE
CoreNet
TM
Coherency Fabric
PAMU
PAMU
PAMU (peripheral access management unit)
FMan
SEC
PME
QMan
BMan
RMan
Parse, classify,
distribute
Buffer
1/10G 1/10G
FMan
Parse, classify,
distribute
Buffer
1/10G 1/10G
InterlakenLA-1
Real-time
debug
3x DMA
SATA 2.0
SATA 2.0
Watch point
cross-
trigger
Perf
Trace
Monitor
sRIO
sRIO
PCle
PCle
PCle
PCle
1G 1G 1G
1G 1G 1G
1G 1G 1G
1G 1G 1G
Aurora
16 lanes up to 10 GHz SerDes
16 lanes up to 10 GHz SerDes
2
1146D–HIREL–10/18
Teledyne e2v Semiconductors SAS 2018
Analog electronics
京公网安备 11010802033920号
EEWORLD
