Integrated
Circuit
Systems, Inc.
ICS9161A
Dual Programmable Graphics Frequency Generator
General Description
The
ICS9161A
is a fully programmable graphics clock
generator. It can generate user-specified clock frequencies
using an externally generated input reference or a single crystal.
The output frequency is programmed by entering a 24-bit
digital word through the serial port. Two fully user-
programmable phase-locked loops are offered in a single
package. One PLL is designed to drive the memory clock,
while the second drives the video clock. The outputs may be
changed on-the-fly to any desired frequency between 390 kHz
and 120 MHz. The
ICS9161A
is ideally suited for any design
where multiple or varying frequencies are required.
This part is ideal for graphics applications. It generates low
jitter, high speed pixel clocks. It can be used to replace multiple,
expensive high speed crystal oscillators. The flexibility of the
device allows it to generate non-standard graphics clocks.
The
ICS9161A
is also ideal in disk drives. It can generate
zone clocks for constant density recording schemes. The low
profile, 16-pin SOIC or PDIP package and low jitter outputs
are especially attractive in board space critical disk drives.
The leader in the area of multiple output clocks on a single
chip, ICS has been shipping graphics frequency generators
since October, 1990, and is constantly improving the phase-
locked loop. The
ICS9161A
incorporates a patented fourth
generation PLL that offers the best jitter performance available.
Features
•
•
•
•
•
•
•
•
•
•
•
Pin-for-pin and function compatible with ICD2061A
Dual programmable graphics clock generator
Memory and video clocks are individually
programmable on-the-fly
Ideal for designs where multiple or varying frequencies
are required
Increased frequency resolution from optional pre-
divide by 2 on the M counter
Output enable feature available for tristating outputs
Independent clock outputs range from 390 kHz to 120
MHz for VDD >4.75V
Power-down capabilities
Low power, high speed 0.8µ CMOS technology
Glitch-free transitions
Available in 16-pin, 300-mil SOIC or PDIP package
Block Diagram
EXTCLK
EXTSEL
D14-D20
7
REF
f
REF
DIVIDE
(M÷)
D4-D10
7
24
24
DECODE
LOGIC
ADDRESS
3
DATA
21
CONTROL REG
21
21
21
VCLK
(D0-D20)
VCO
DIVIDE
(N÷)
D0-D3
4
D11-D13
3
CMOS
OUTPUT
DRIVER
X1
X2
XTAL
OSC
VCO
VCO OUTPUT
DIVIDER
R=1,2,4,8,16
32,64,128
MUX
VCLK
SEL0-CLK
SEL1-DATA
REGISTERS
3-TO-1
MUX
21
Pscale
P= 2 or 4
OE
21
MCLK
(D0-D20)
D14-D20
7
REF
DIVIDE
(M÷)
D4-D10
7
D0-D3
4
D11-D13
3
INIT1
INIT2
INIT
ROM
VCO
VCO OUTPUT
DIVIDER
R=1,2,4,8,16
32,64,128
CMOS
OUTPUT
DRIVER
MCLK
POR
PD
VCO
DIVIDE
(N÷)
Pscale
P= 2
9161-A RevG 10/04/00
9161
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS9161A
Pin Configuration
16-Pin 300- mil SOIC or PDIP
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN NAME
SEL0-CLK
SEL1-DATA
AVDD
OE
GND
X1
X2
MCLK
VCLK
ERROUT#
EXTCLK
INIT0
VDD
INIT1
EXTSEL
PD#
TYPE
IN
IN
PWR
IN
PWR
IN
OUT
OUT
OUT
OUT
IN
IN
PWR
IN
IN
IN
DESCRIPTION
Clock input in serial programming mode. Clock select pin in operating mode.
Has internal pull-down to GND.
Data input in serial programming mode. Clock select pin in operating mode. Has
internal pull-down to GND.
Power.
Tristates outputs when low. Has internal pull-up to VDD.
Ground.
Crystal input. This input includes XTAL load capacitance and feedback bias for
the crystal.
Crystal output which includes internal XTAL load capacitance.
Memory clock output.
Video clock output.
Output low signals an error in the serially programmed word.
External clock input. Has internal pull-up to VDD.
Selects initial power-up conditions, LSB. Has internal pull-down to GND.
Power.
Selects initial power-up conditions, MSB. Has internal pull-down to GND.
Selects external clock input (EXTCLK) as VCLK output. Has internal pull-up to
VDD.
Power-down pin, active low. Has internal pull-up to VDD.
2
ICS9161A
Register Definitions
The register file consists of the following six registers:
Register Addressing
Address
(A2 - A0)
000
001
010
011
100
110
Register
REG0
REG1
REG2
MREG
PWRDWN
CNTL REG
Definition
Video Clock Register 1
Video Clock Register 2
Video Clock Register 3
Memory Register
Divisor for Power-down mode
Control Register
As seen in the VCLK Selection table, OE acts to tristate the
output. The PD# pin forces the VCLK signal high while
powering down the part. The EXTCLK pin will only be
multiplexed in when EXTSEL and SEL0 are logic 0 and SEL1
is a logic 1.
The memory clock outputs are controlled by PD# and OE
as follows:
MCLK Selection
OE
0
1
1
PD#
x
1
0
MCLK
Tristate
MREG
PWRDWN
The
ICS9161A
places the three video clock registers and the
memory clock register in a known state upon power-up. The
registers are initialized based on the state of the INIT1 and
INIT0 pins at application of power to the device. The INIT pins
must ramp up with VDD if a logical 1 on either pin is required.
These input pins are internally pulled down and will default to
a logical 0 if left unconnected.
The registers are initialized as follows:
Register Initialization
INIT1
0
0
1
1
INIT0
0
1
0
1
MREG
32.500
40.000
50.350
56.644
REG0
25.175
25.175
40.000
40.000
REG1
28.322
28.322
28.322
50.350
REG2
28.322
28.322
28.322
50.350
The Clock Select pins SEL0 and SEL1 have two purposes. In
serial programming mode, these pins act as the clock and data
pins. New data bits come in on SEL1 and these bits are
clocked in by a signal on SEL0. While these pins are acquiring
new information, the VCLK signal remains unchanged. When
SEL0 and SEL1 are acting as register selects, a time-out
interval is required to determine whether the user is selecting
a new register or wants to program the part. During this initial
time-out, the VCLK signal remains at its previous frequency.
At the end of this time-out interval, a new register is selected.
A second time-out interval is required to allow the VCO to
settle to its new value. During this period of time, typically
5ms, the input reference signal is multiplexed to the VCLK
signal.
When MCLK or the active VCLK register is being re-
programmed, then the reference signal is multiplexed glitch-
free to the output during the first time-out interval. A second
time-Register out interval is also required to allow the VCO
to settle. During this period, the reference signal is
multiplexed to the appropriate output signal.
Register Selection
When the
ICS9161A
is operating, the video clock output is
controlled with a combination of the SEL0, SEL1, PD# and
OE pins. The video clock is also multiplexed to an external
clock (EXTCLK) which can be selected with the EXTSEL
pin. The VCLK Selection Table shows how VCLK is selected.
VCLK Selection
OE
0
1
1
1
1
1
1
PD#
x
0
1
1
1
1
1
EXTSEL
x
x
x
x
0
1
x
SEL1 SEL0
x
x
0
0
1
1
1
x
x
0
1
0
x
1
VCLK
Tristate
Forced High
REG0
REG1
EXTCLK
REG2
REG2
3
ICS9161A
Control Register Definitions
The control register allows the user to adjust various internal options. The register is defined as follows:
Bit
Bit Name
Default Value
Description
This bit determines which power-down mode the PD# pin will implement.
Power-down mode 1, C5=0, forces the MCLK signals to be a function of the
power-down register. Power-down mode 2, C5=1, turns off the crystal and
disables all outputs.
This bit determines which clock is multiplexed to VCLK during frequency
changes. C4=0 multiplexes the reference frequency to the VCLK output. C4=1
multiplexes MCLK to the VCLK output for applications where the graphics
controller cannot run as slow as f
REF.
This bit determines the length of the time-out interval. The time-out interval is
derived from the MCLK VCO. If this VCO is programmed to certain extremes,
the time-out interval may be too short. C3=0, normal time-out. C3=1, doubled
time-out interval.
Reserved, must be set to 0.
This bit adjusts the duty cycle. C1=0 causes a 1ns decrease in output high time.
C1=1 causes no adjustment. If the load capacitance is high, the adjustment can
bring the duty cycle closer to 50%.
Reserved, must be set to 0.
Acts on register 2. NS2=0 prescales the N counter by 2. NS2=1 prescales the P
counter value to 4.
Acts on register 1. NS1=0 prescales the N counter by 2. NS1=1 prescales the P
counter value to 4.
Acts on register 0. NS1=0 prescales the N counter by 2. NS0=1 prescales the P
counter value to 4.
21
C5
0
20
C4
0
19
18
17
16
15
14
13
C3
C2
C1
C0
NS2
NS1
NS0
0
0
1
0
0
0
0
4
ICS9161A
Serial Programming Architecture
The pins SEL0 and SEL1 perform the dual functions of select-
ing registers and serial programming. In serial programming
mode, SEL0 acts as a clock pin while SEL1 acts as the data pin.
The ICS9161A-01
may not be serially programmed when in
power-down mode.
In order to program a particular register, an unlocking sequence
must occur. The unlocking sequence is detailed in the following
timing diagram:
Since the VCLK registers are selected by the SEL0 and SEL1
pins, and since any change in their state may affect the output
frequency, new data input on the selection bits is only permitted
to pass through the decode logic after the watchdog timer has
timed out. This delay of SEL0 or SEL1 data permits a serial
program cycle to occur without affecting the current register
selection.
Serial Data Register
The serial data is clocked into the serial data register in the
order described in Figure 1 below (Serial Data Timing).
The serial data is sent as follows: An individual data bit is
sampled on the rising edge of CLK. The complement of the
data bit must be sampled on the previous falling edge of CLK.
The setup and hold time requirements must be met on both
CLK edges. For specifics on timing, see the timing diagrams
on pages 10, 11 and 12.
The unlock sequence consists of at least five low-to-high
transitions of CLK while data is high, followed immediately
by a single low-to-high transition while data is low. Following
this unlock sequence, data can be loaded into the serial data
register. This programming must include the start bit, shown
in Figure 1.
Following any transition of CLK or DATA, the watchdog
timer is reset and begins counting. The watchdog timer
ensures that successive rising edges of CLK and DATA do not
violate the time-out specification of 2ms. If a time-out
occurs, the lock mechanism is reset and the data in the serial
data register is ignored.
The bits are shifted in this order: a start bit, 21 data bits, 3
address bits (which designate the desired register), and a stop
bit. A total of 24 bits must always be loaded into the serial data
register or an error is issued. Following the entry of the last
data bit, a stop bit or load command is issued by bringing
DATA high and toggling CLK high-to-low and low-to-high.
The unlocking mechanism then resets itself following the
load. Only after a time-out period are the SEL0 and SEL1 pins
allowed to return to a register selection function.
Figure 1: Serial Data Timing
5
京公网安备 11010802033920号
EEWORLD
