74VHC74 Dual D-Type Flip-Flop with Preset and Clear
October 1992
Revised February 2005
74VHC74
Dual D-Type Flip-Flop with Preset and Clear
General Description
The VHC74 is an advanced high speed CMOS Dual D-
Type Flip-Flop fabricated with silicon gate CMOS technol-
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The signal level applied to the D input is
transferred to the Q output during the positive going transi-
tion of the CK pulse. CLR and PR are independent of the
CK and are accomplished by setting the appropriate input
LOW.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: f
MAX
170 MHz (typ) at T
A
V
NIL
25
q
C
s
High noise immunity: V
NIH
s
Low power dissipation: I
CC
28% V
CC
(min)
25
q
C
s
Power down protection is provided on all inputs
2
P
A (max) at T
A
s
Pin and function compatible with 74HC74
Ordering Code:
Order Number
74VHC74M
74VHC74MX_NL
74VHC74SJ
74VHC74MTC
74VHC74MTCX_NL
(Note 1)
74VHC74N
Package
Number
M14A
M14A
M14D
MTC14
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDED J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS011505
www.fairchildsemi.com
74VHC74
Absolute Maximum Ratings
(Note 3)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Input Diode Current (I
IK
)
Output Diode Current (I
OK
)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
Soldering (10 seconds)
260
q
C
0.5V to
7.0V
0.5V to
7.0V
0.5V to V
CC
0.5V
20 mA
r
20 mA
r
25 mA
r
50 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 4)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
V
CC
3.3V
r
0.3V
5.0V
r
0.5V
0
a
100 ns/V
0
a
20 ns/V
2.0V to 5.5V
0V to
5.5V
0V to V
CC
40
q
C to
85
q
C
Note 3:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading varai-
bles. Fairchild does not recommend operation outside databook specifica-
tions.
Note 4:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input
Voltage
LOW Level Input
Voltage
HIGH Level Output
Voltage
V
CC
(V)
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
4.5
V
OL
LOW Level Output
Voltage
2.0
3.0
4.5
3.0
4.5
I
IN
I
CC
Input Leakage Current
Quiescent Supply Current
0
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
2.0
3.0
4.5
T
A
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
V
I
OL
I
OL
V
IN
V
IN
4 mA
8 mA
V
V
V
IN
I
OH
I
OH
V
IH
I
OL
or V
IL
V
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
Min
1.50
0.7 V
CC
Units
V
Conditions
0.50
0.3 V
CC
V
V
IN
V
IH
I
OH
or V
IL
50
P
A
4 mA
8 mA
50
P
A
r
0.1
2.0
r
1.0
20.0
P
A
P
A
5.5V or GND
V
CC
or GND
3
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74VHC74
AC Electrical Characteristics
Symbol
f
MAX
Parameter
Maximum Clock
Frequency
5.0
r
0.5
t
PLH
t
PHL
Propagation Delay
Time (CK-Q, Q)
5.0
r
0.5
t
PLH
t
PHL
Propagation Delay Time
(CLR, PR -Q, Q)
5.0
r
0.5
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
Note 5:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: I
CC
(opr.) C
PD
* V
CC
* f
IN
I
CC
/2 (per F/F).
V
CC
(V)
3.3
r
0.3
T
A
Min
80
50
130
90
25
q
C
Typ
125
75
170
115
6.7
9.2
4.6
6.1
7.6
10.1
4.8
6.3
4
25
11.9
15.4
7.3
9.3
12.3
15.8
7.7
9.7
10
Max
T
A
40
q
C to
85
q
C
Max
70
45
Min
Units
MHz
MHz
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
Conditions
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
Open
110
75
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
14.0
17.5
8.5
10.5
14.5
18.0
9.0
11.0
10
3.3
r
0.3
ns
ns
ns
ns
pF
pF
3.3
r
0.3
V
CC
(Note 5)
AC Operating Requirements
Symbol
t
W
(L)
t
W
(H)
t
W
(L)
t
S
t
H
Minimum Pulse Width (CLR, PR)
Minimum Setup Time
Minimum Hold Time
Parameter
Minimum Pulse Width (CK)
V
CC
(V)
(Note 6)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
t
REC
Minimum Recovery Time (CLR, PR)
3.3
5.0
Note 6:
V
CC
is 3.3
r
0.3V or 5.0
r
0.5V
T
A
Typ
25
q
C
T
A
40
q
C to
85
q
C
Units
Guaranteed Minimum
6.0
5.0
6.0
5.0
6.0
5.0
0.5
0.5
5.0
3.0
7.0
5.0
7.0
5.0
7.0
5.0
0.5
0.5
5.0
3.0
ns
ns
ns
ns
ns
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