HUF76013P3, HUF76013D3S
Data Sheet
October 2004
20A, 20V, 0.022 Ohm, N-Channel, Logic
Level Power MOSFETs
The HUF76013 is an application-specific MOSFET
optimized for switching when used as the upper switch in
synchronous buck applications. The low gate charge and low
input capacitance results in lower driver and lower switching
losses thereby increasing the overall system efficiency.
Features
• 20A, 20V
- r
DS(ON)
= 0.022Ω, V
GS
=
10V
- r
DS(ON)
= 0.030Ω, V
GS
=
5V
• PWM Optimized for Synchronous Buck Applications
• Fast Switching
Symbol
D
G
• Low Gate Charge
- Q
g
Total 14nC (Typ)
S
Packaging
HUF76013D3S
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
HUF76013P3
JEDEC TO-220AB
SOURCE
DRAIN
GATE
• Low Capacitance
- C
ISS
624pF (Typ)
- C
RSS
71pF (Typ)
Ordering Information
PART NUMBER
HUF76013P3
HUF76013D3S
PACKAGE
TO-220AB
TO-252AA
BRAND
76013P
76013D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the HUF76013D3S in tape and reel, e.g., HUF76013D3ST.
Absolute Maximum Ratings
SYMBOL
V
DSS
V
DGR
V
GS
I
D
I
D
I
DM
P
D
T
J
, T
STG
T
L
T
pkg
R
θJC
R
θJA
NOTE:
1. T
J
= 25
o
C to 125
o
C.
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
HUF76013P3,
HUF76013D3S
20
20
±20
20
20
Figure 4
50
0.4
-55 to 150
300
260
2.5
62
100
UNITS
V
V
V
A
A
A
W
W/
o
C
o
C
o
C
o
C
o
C/W
o
C/W
o
C/W
Drain to Source Voltage (Note 1)
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1)
Gate to Source Voltage
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2)
Continuous (T
C
= 100
o
C, V
GS
= 5V)
Pulsed Drain Current
Power Dissipation
Derate Above 25
o
C
Operating and Storage Temperature
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s
Package Body for 10s, See Techbrief TB334
Thermal Resistance Junction to Case, TO-220, TO-252
Thermal Resistance Junction to Ambient TO-220
Thermal Resistance Junction to Ambient TO-252
THERMAL SPECIFICATIONS
CAUTION:
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
©2004 Fairchild Semiconductor Corporation
HUF76013P3, HUF76013D3S Rev. C
HUF76013P3, HUF76013D3S
Electrical Specifications
PARAMETER
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
DSS
I
DSS
I
GSS
V
GS(TH)
r
DS(ON)
I
D
= 250µA, V
GS
= 0V (Figure 11)
V
DS
= 20V, V
GS
= 0V
V
DS
= 20V, V
GS
= 0V, T
C
= 150
o
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source ON Resistance
V
GS
= V
DS
, I
D
= 250µA (Figure 10)
I
D
= 20A, V
GS
= 10V (Figures 8, 9)
I
D
= 20A, V
GS
= 5V (Figure 8)
SWITCHING SPECIFICATIONS
(V
GS
= 5V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Q
g(TOT)
Q
g(TOT)
Q
g(TH)
Q
gs
Q
gd
C
ISS
C
OSS
C
RSS
V
DS
= 20V, V
GS
= 0V,
f = 1MHz
(Figure 12)
V
GS
= 0V to 10V
V
GS
= 0V to 5V
V
GS
= 0V to 1V
V
DD
= 10V,
I
D
= 20A,
I
g(REF)
= 1.0mA
(Figures 13, 16, 17)
V
DD
= 10V, I
D
= 20A
V
GS
=
10V,
R
GS
= 19Ω
(Figures 15, 18, 19)
V
DD
= 10V, I
D
= 20A
V
GS
=
5V, R
GS
= 19Ω
(Figures 14, 18, 19)
-
-
-
-
-
-
-
11
120
19
30
-
197
-
-
-
-
72
ns
ns
ns
ns
ns
ns
1
-
-
-
0.018
0.025
3
0.022
0.030
V
Ω
Ω
V
GS
=
±20V
20
-
-
-
-
-
-
-
-
1
250
±100
V
µA
µA
nA
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge at 10V
Total Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
-
-
-
624
444
71
-
-
-
pF
pF
pF
-
-
-
-
-
14.4
7.8
0.9
3.5
3.2
17
9
1
-
-
nC
nC
nC
nC
nC
-
-
-
-
-
-
-
7
93
37
29
-
151
-
-
-
-
100
ns
ns
ns
ns
ns
ns
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
SYMBOL
V
SD
t
rr
Q
RR
I
SD
= 20A
I
SD
= 10A
Reverse Recovery Time
Reverse Recovered Charge
I
SD
= 20A, dI
SD
/dt = 100A/µs
I
SD
= 20A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
-
TYP
-
-
-
-
MAX
1.25
1.0
55
82
UNITS
V
V
ns
nC
©2004 Fairchild Semiconductor Corporation
HUF76013P3, HUF76013D3S Rev. C
HUF76013P3, HUF76013D3S
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
0
0
25
50
75
100
125
150
25
50
75
100
125
150
T
A
, AMBIENT TEMPERATURE (
o
C)
T
C
, CASE TEMPERATURE (
o
C)
I
D
, DRAIN CURRENT (A)
25
V
GS
= 10V
20
V
GS
= 5.0V
15
10
5
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
THERMAL IMPEDANCE
Z
θJC
, NORMALIZED
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
SINGLE PULSE
0.01
10
-5
10
-4
10
-3
10
-2
t, RECTANGULAR PULSE DURATION (s)
10
-1
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
0
10
1
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000
T
C
= 25
o
C
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
V
GS
= 10V
I = I
25
150 - T
C
125
I
DM
, PEAK CURRENT (A)
100
V
GS
= 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10
-5
10
-4
10
-3
10
-2
t, PULSE WIDTH (s)
10
-1
10
0
10
1
FIGURE 4. PEAK CURRENT CAPABILITY
©2004 Fairchild Semiconductor Corporation
HUF76013P3, HUF76013D3S Rev. C
HUF76013P3, HUF76013D3S
Typical Performance Curves
300
(Continued)
40
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
30
I
D
, DRAIN CURRENT (A)
100µs
I
D
, DRAIN CURRENT (A)
100
20
T
J
= 150
o
C
10
T
J
= 25
o
C
0
T
J
= -55
o
C
5
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
SINGLE PULSE
T
J
= MAX RATED T
C
= 25
o
C
1ms
10ms
1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
50
2
3
4
V
GS
, GATE TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. TRANSFER CHARACTERISTICS
40
V
GS
= 10V
I
D
, DRAIN CURRENT (A)
30
V
GS
= 5V
r
DS(ON)
, DRAIN TO SOURCE
ON RESISTANCE (mΩ)
T
C
= 25
o
C
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
GS
= 4V
50
I
D
= 20A
40
I
D
= 5A
30
I
D
= 10A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
20
V
GS
= 3.5V
10
V
GS
= 3V
0
20
10
0
1
2
3
4
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
2
4
6
8
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.6
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED GATE
THRESHOLD VOLTAGE
1.4
1.2
V
GS
= V
DS
, I
D
= 250µA
1.0
1.2
1.0
0.8
0.8
V
GS
= 10V, I
D
= 20A
0.6
-80
-40
0
40
80
120
160
0.6
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2004 Fairchild Semiconductor Corporation
HUF76013P3, HUF76013D3S Rev. C
HUF76013P3, HUF76013D3S
Typical Performance Curves
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
I
D
= 250µA
C, CAPACITANCE (pF)
1.1
1000
C
ISS
=
C
GS
+ C
GD
(Continued)
2500
C
OSS
≅
C
DS
+ C
GD
1.0
C
RSS
=
C
GD
0.9
100
V
GS
= 0V, f = 1MHz
-40
0
40
80
120
160
50
0.1
1
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10
20
T
J
, JUNCTION TEMPERATURE (
o
C)
0.8
-80
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DD
= 10V
8
SWITCHING TIME (ns)
180
V
GS
= 5V, V
DD
= 10V, I
D
= 20A
150
t
r
120
90
60
30
t
d(ON)
15
0
0
10
20
30
40
50
R
GS
, GATE TO SOURCE RESISTANCE (Ω)
t
f
t
d(OFF)
6
4
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 20A
I
D
= 10A
I
D
= 5A
0
3
6
9
12
2
0
Q
g
, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
120
V
GS
= 10V, V
DD
= 10V, I
D
= 20A
100
SWITCHING TIME (ns)
80
60
40
20
0
0
10
20
30
40
50
t
r
t
d(OFF)
t
f
t
d(ON)
R
GS
, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
©2004 Fairchild Semiconductor Corporation
HUF76013P3, HUF76013D3S Rev. C
京公网安备 11010802033920号
EEWORLD
