DS2151Q
T1 Single-Chip Transceiver
www.dalsemi.com
FEATURES
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
Complete DS1/ISDN-PRI transceiver
functionality
Line interface can handle both long- and
short-haul trunks
32-bit or 128-bit jitter attenuator
Generates DSX-1 and CSU line build outs
Frames to D4, ESF, and SLC-96
R
formats
Dual onboard two-frame elastic store slip
buffers that connect to backplanes up to 8.192
MHz
8-bit parallel control port that can be used on
either multiplexed or non-multiplexed buses
Extracts and inserts Robbed-Bit signaling
Detects and generates yellow and blue alarms
Programmable output clocks for Fractional T1
Fully independent transmit and receive
functionality
Onboard FDL support circuitry
Generates and detects CSU loop codes
Contains ANSI one’s density monitor and
enforcer
Large path and line error counters including
BPV, CV, CRC6, and framing bit errors
Pin compatible with DS2153Q E1 Single-
Chip Transceiver
5V supply; low power CMOS
Industrial grade version (-40°C to +85°C)
available (DS2151QN)
PIN ASSIGNMENT
FUNCTIONAL BLOCKS
LONG & SHORT
HAUL LINE
INTERFACE
FRAMER
PARALLEL CONTROL
PORT
Dallas
DS2151Q
T1SCT
ACTUAL SIZE OF 44-PIN PLCC
TCHCLK
40
39
38
37
36
35
34
33
32
31
30
29
19
20
21
22
23
24
25
26
27
28
AD7
AD6
AD5
AD4
AD3
AD2
43
AD1
42
ALE
WR
RLINK
RLCLK
DVSS
RCLK
RCHCLK
RSER
RSYNC
RLOS/LOTC
SYSCLK
44
41
6
5
4
3
2
1
AD0
RD
CS
ELASTIC
STORES
7
8
9
10
11
12
13
14
15
16
17
18
TSER
TCLK
DVDD
TSYNC
TLINK
TLCLK
TCHBLK
TRING
TVDD
TVSS
TTIP
INT1
XTAL1
RRING
DESCRIPTION
The DS2151Q T1 Single-Chip Transceiver (SCT) contains all of the necessary functions for connection
to T1 lines whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry
automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both
DSX-1 line build outs as well as CSU build outs of -7.5 dB, -15 dB, and -22.5 dB. The onboard jitter
attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms.
It is also used for extracting and inserting Robbed-Bit signaling data and FDL data. The device contains
a set of 64 8-bit internal registers which the user can access to control the operation of the unit. Quick
access via the parallel control port allows a single micro to handle many T1 lines. The device fully meets
all of the latest T1 specifications including ANSI T1.403-199X, AT&T TR 62411 (12-90), and ITU
G.703, G.704, G.706, G.823, and I.431.
1 of 51
081099
RCHBLK
XTAL2
ACLKI
RTIP
RVDD
RVSS
INT2
BTS
DS2151Q
TABLE OF CONTENTS
1. Introduction
2. Parallel Control Port
3. Control Registers
4. Status and Information Registers
5. Error Count Registers
6. FDL/Fs Extraction/Insertion
7. Signaling Operation
8. Transmit Transparency and Idle Registers
9. Clock Blocking Registers
10. Elastic Stores Operation
11. Receive Mark Registers
12. Line Interface Functions
13. Timing Diagrams and Transmit Flow Diagram
14. DC and AC Characteristics
1.0
INTRODUCTION
The analog AMI waveform off of the T1 line is transformer coupled into the RRING and RTIP pins of
the DS2151Q. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing
pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered T1 data stream and an asynchronous backplane clock which is
provided at the SYSCLK input.
The transmit side of the DS2151Q is totally independent from the receive side in both the clock
requirements and characteristics. Data can be either provided directly to the transmit formatter or via an
elastic store. The transmit formatter will provide the necessary data overhead for T1 transmission. Once
the data stream has been prepared for transmission, it is sent via the jitter attenuation mux to the
waveshaping and line driver functions. The DS2151Q will drive the T1 line from the TTIP and TRING
pins via a coupling transformer.
2 of 51
DS2151Q
DS2151Q BLOCK DIAGRAM
Figure 1-1
3 of 51
DS2151Q
PIN DESCRIPTION
Table 1-1
PIN
1
2
3
4
5
6
7
8
9
SYMBOL
AD4
AD5
AD6
AD7
RD
(DS)
CS
TYPE
I/O
DESCRIPTION
Address/Data Bus.
An 8-bit multiplexed address/data bus.
ALE(AS)
WR
(R/
W
)
I
I
I
I
O
RLINK
10
11
12
13
RLCLK
DVSS
RCLK
RCHCLK
O
-
O
O
14
15
RSER
RSYNC
O
I/O
16
RLOS/LOTC
O
17
SYSCLK
I
18
RCHBLK
O
Read Input (Data Strobe).
Chip Select.
Must be low to read or write the port.
Address Latch Enable (Address Strobe).
A positive going edge
serves to demultiplex the bus.
Write Input (Read/Write).
Receive Link Data.
Updated with either FDL data (ESF) or Fs bits
(D4) or Z bits (ZBTSI) one RCLK before the start of a frame. See
Section 13 for timing details.
Receive Link Clock.
4 kHz or 2 kHz (ZBTSI) demand clock for the
RLINK output. See Section 13 for timing details.
Digital Signal Ground.
0.0 volts. Should be tied to local ground plane.
Receive Clock.
Recovered 1.544 MHz clock.
Receive Channel Clock.
192 kHz clock which pulses high during the
LSB of each channel. Useful for parallel to serial conversion of channel
data, locating Robbed-Bit signaling bits, and for blocking clocks in
DDS applications. See Section 13 for timing details.
Receive Serial Data.
Received NRZ serial data, updated on rising
edges of RCLK or SYSCLK.
Receive Sync.
An extracted pulse, one RCLK wide, is output at this
pin which identifies either frame (RCR2.4=0) or multiframe boundaries
(RCR2.4=1). If set to output frame boundaries, then via RCR2.5,
RSYNC can also be set to output double-wide pulses on signaling
frames. If the elastic store is enabled via the CCR1.2, then this pin can
be enabled to be an input via RCR2.3 at which a frame boundary pulse
is applied. See Section 13 for timing details.
Receive Loss of Sync/Loss of Transmit Clock.
A dual function
output. If CCR3.5=0, will toggle high when the synchronizer is
searching for the T1 frame and multiframe; if CCR3.5=1, will toggle
high if the TCLK pin has not toggled for 5 us.
System Clock.
1.544 MHz or 2.048 MHz clock. Only used when the
elastic store functions are enabled via either CCR1.7 or CCR1.2.
Should be tied low in applications that do not use the elastic store. If
tied high for more than 100 us, will force all output pins (including the
parallel port) to 3-state.
Receive Channel Block.
A user programmable output that can be
forced high or low during any of the 24 T1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in applications
where not all T1 channels are used such as Fractional T1, 384k bps
service, 768k bps, or ISDN-PRI. Also useful for locating individual
channels in drop-and-insert applications. See Section 13 for timing
details.
4 of 51
DS2151Q
PIN
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
SYMBOL TYPE
DESCRIPTION
ACLKI
I
Alternate Clock Input.
Upon a receive carrier loss, the clock applied at
this pin (normally 1.544 MHz) will be routed to the RCLK pin. If no
clock is routed to this pin, then it should be tied to DVSS VIA A1K Ohm
RESISTOR.
BTS
I
Bus Type Select.
Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the
RD
(DS),
ALE(AS), and
WR
(R/
W
) pins. If BTS=1, then these pins assume the
function listed in parenthesis ().
RTIP
-
Receive Tip and Ring.
Analog inputs for clock recovery circuitry;
RRING
connects to a 1:1 transformer (see Section 12 for details).
RVDD
-
Receive Analog Positive Supply.
5.0 volts. Should be tied to DVDD
and TVDD pins.
RVSS
-
Receive Signal Ground.
0.0 volts. Should be tied to local ground plane
XTAL1
-
Crystal Connections.
A pullable 6.176 MHz crystal must be applied to
XTAL2
these pins. See Section 12 for crystal specifications.
O
Receive Alarm Interrupt 1.
Flags host controller during alarm
INT1
conditions defined in Status Register 1. Active low, open drain output.
O
Receive Alarm Interrupt 2.
Flags host controller during conditions
INT2
defined in Status Register 2. Active low, open drain output.
TTIP
-
Transmit Tip.
Analog line driver output; connects to a step-up
transformer (see Section 12 for details).
TVSS
-
Transmit Signal Ground.
0.0 volts. Should be tied to local ground
plane.
TVDD
-
Transmit Analog Positive Supply.
5.0 volts. Should be tied to DVDD
and RVDD pins.
TRING
-
Transmit Ring.
Analog line driver outputs; connects to a step-up
transformer (see Section 12 for details).
TCHBLK
O
Transmit Channel Block.
A user programmable output that can be
forced high or low during any of the 24 T1 channels. Useful for blocking
clocks to a serial UART or LAPD controller in applications where not all
T1 channels are used such as Fractional T1, 384k bps service, 768k bps,
or ISDN-PRI. Also useful for locating individual channels in drop-and-
insert applications. See Section 13 for timing details.
TLCLK
O
Transmit Link Clock.
4 kHz or 2 kHz (ZBTSI) demand clock for the
TLINK input. See Section 13 for timing details.
TLINK
I
Transmit Link Data.
If enabled via TCR1.2, this pin will be sampled
during the F-bit time on the falling edge of TCLK for data insertion into
either the FDL stream (ESF) or the Fs bit position (D4) or the Z-bit
position (ZBTSI). See Section 13 for timing details.
TSYNC
I/O
Transmit Sync.
A pulse at this pin will establish either frame or
multiframe boundaries for the DS2151Q. Via TCR2.2, the DS2151Q can
be programmed to output either a frame or multiframe pulse at this pin. If
this pin is set to output pulses at frame boundaries, it can also be set via
TCR2.4 to output double-wide pulses at signaling frames. See Section 13
for timing details.
DVDD
-
Digital Positive Supply.
5.0 volts. Should be tied to RVDD and TVDD
pins.
5 of 51
京公网安备 11010802033920号
EEWORLD
