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MACH231SP-15VC

Description
High-Performance EE CMOS Programmable Logic
CategoryProgrammable logic devices    Programmable logic   
File Size504KB,48 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Download Datasheet Parametric View All

MACH231SP-15VC Overview

High-Performance EE CMOS Programmable Logic

MACH231SP-15VC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerLattice
package instructionTQFP-100
Reach Compliance Code_compli
ECCN codeEAR99
Other featuresYES
maximum clock frequency50 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G100
JESD-609 codee0
JTAG BSTNO
length14 mm
Humidity sensitivity level3
Dedicated input times2
Number of I/O lines64
Number of macro cells128
Number of terminals100
Maximum operating temperature70 °C
Minimum operating temperature
organize2 DEDICATED INPUTS, 64 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP100,.63SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
power supply5 V
Programmable logic typeEE PLD
propagation delay15 ns
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
width14 mm
MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmab
FEATURES
x
x
x
x
x
x
x
x
x
x
x
x
x
High-performance electrically-erasable CMOS PLD families
32 to 128 macrocells
44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages
SpeedLocking™ – guaranteed fixed timing up to 16 product terms
Commercial 5/5.5/6/7.5/10/12/15-ns t
PD
and Industrial 7.5/10/12/14/18-ns t
PD
Configurable macrocells
— Programmable polarity
— Registered or combinatorial outputs
— Internal and I/O feedback paths
— D-type or T-type flip-flops
— Output Enables
— Choice of clocks for each flip-flop
— Input registers for MACH 2 family
JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available
Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns
Safe for mixed supply voltage system designs
Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs
Programmable power-down mode results in power savings of up to 75%
Supported by Vantis DesignDirect™ software for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Lattice/Vantis and third-party hardware programming support
— Lattice/VantisPRO™ (formerly known as MACHPRO
®
) software for in-system program
support on PCs and Automated Test Equipment
— Programming support on all major programmers including Data I/O, BP Microsystem
and System General
Publication#
14051
Amendment/0
Rev:
K
Issue Date:
November 1998
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