MACH231-10JC/1 datasheet, PDF - EEWORLD Datasheet

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MACH231-10JC/1: DescriptionHigh-Performance EE CMOS Programmable Logic; CategoryProgrammable logic devices Programmable logic; File Size504KB，48 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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MACH231-10JC/1 Overview

High-Performance EE CMOS Programmable Logic

MACH231-10JC/1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	LCC
package instruction	PLASTIC, LCC-84
Contacts	84
Reach Compliance Code	unknow
ECCN code	EAR99
Other features	NO
maximum clock frequency	77 MHz
In-system programmable	NO
JESD-30 code	S-PQCC-J84
JESD-609 code	e0
JTAG BST	NO
length	29.3116 mm
Humidity sensitivity level	3
Dedicated input times	2
Number of I/O lines	64
Number of macro cells	128
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2 DEDICATED INPUTS, 64 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC84,1.2SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Programmable logic type	EE PLD
propagation delay	10 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	29.3116 mm

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MACH 1 and 2 CPLD Families

High-Performance EE CMOS Programmab

FEATURES

High-performance electrically-erasable CMOS PLD families

32 to 128 macrocells

44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages

SpeedLocking™ – guaranteed ﬁxed timing up to 16 product terms

Commercial 5/5.5/6/7.5/10/12/15-ns t

and Industrial 7.5/10/12/14/18-ns t

Conﬁgurable macrocells

— Programmable polarity

— Registered or combinatorial outputs

— Internal and I/O feedback paths

— D-type or T-type ﬂip-ﬂops

— Output Enables

— Choice of clocks for each ﬂip-ﬂop

— Input registers for MACH 2 family

JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available

Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns

Safe for mixed supply voltage system designs

Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs

Programmable power-down mode results in power savings of up to 75%

Supported by Vantis DesignDirect™ software for rapid logic development

— Supports HDL design methodologies with results optimized for Vantis

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

Lattice/Vantis and third-party hardware programming support

— Lattice/VantisPRO™ (formerly known as MACHPRO

) software for in-system program

support on PCs and Automated Test Equipment

— Programming support on all major programmers including Data I/O, BP Microsystem

and System General

Publication#

14051

Amendment/0

Rev:

Issue Date:

November 1998

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