MACH230-10 datasheet, PDF - EEWORLD Datasheet

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MACH230-10: DescriptionHigh-Density EE CMOS Programmable Logic; File Size151KB，29 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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MACH230-10 Overview

High-Density EE CMOS Programmable Logic

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FINAL

COM’L: -10/15/20

IND: -18/24

MACH230-10/15/20

High-Density EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

84 Pins

128 Macrocells

10 ns t

Commercial

18 ns t

Industrial

100 MHz f

CNT

70 Inputs

64 Outputs

Lattice Semiconductor

128 Flip-flops; 4 clock choices

8 “PAL26V16” blocks with buried macrocells

Pin-compatible with MACH130, MACH131,

MACH231, and MACH435

GENERAL DESCRIPTION

The MACH230 is a member of the high-performance

EE CMOS MACH 2 device family. This device has ap-

proximately twelve times the logic macrocell capability

of the popular PAL22V10 without loss of speed.

The MACH230 consists of eight PAL blocks intercon-

nected by a programmable switch matrix. The switch

matrix connects the PAL blocks to each other and to all

input pins, providing a high degree of connectivity be-

tween the fully-connected PAL blocks. This allows

designs to be placed and routed efficiently.

The MACH230 has two kinds of macrocell: output and

buried. The output macrocell provides registered,

latched, or combinatorial outputs with programmable

polarity. If a registered configuration is chosen, the reg-

ister can be configured as D-type or T-type to help

reduce the number of product terms. The register type

decision can be made by the designer or by the soft-

ware. All output macrocells can be connected to an I/O

cell. If a buried macrocell is desired, the internal feed-

back path from the macrocell can be used, which frees

up the I/O pin for use as an input.

The MACH230 has dedicated buried macrocells which,

in addition to the capabilities of the output macrocell,

also provide input registers for use in synchronizing

signals and reducing setup time requirements.

BLOCK DIAGRAM

If you would like to view

Block Diagram in full size,

please click on the box.

Publication#

14132

Rev.

Issue Date:

May 1995

Amendment

MACH230-10 Related Products

	MACH230-10	MACH230-15JC	MACH230-20JC	MACH230-10JC
Description	High-Density EE CMOS Programmable Logic	High-Density EE CMOS Programmable Logic	High-Density EE CMOS Programmable Logic	High-Density EE CMOS Programmable Logic
Is it Rohs certified?	-	incompatible	incompatible	incompatible
Maker	-	Lattice	Lattice	Lattice
Parts packaging code	-	LCC	LCC	LCC
package instruction	-	QCCJ, LDCC84,1.2SQ	QCCJ, LDCC84,1.2SQ	PLASTIC, LCC-84
Contacts	-	84	84	84
Reach Compliance Code	-	_compli	compli	unknow
ECCN code	-	EAR99	EAR99	EAR99
Other features	-	NO	NO	NO
maximum clock frequency	-	50 MHz	40 MHz	77 MHz
In-system programmable	-	NO	NO	NO
JESD-30 code	-	S-PQCC-J84	S-PQCC-J84	S-PQCC-J84
JESD-609 code	-	e0	e0	e0
JTAG BST	-	NO	NO	NO
length	-	29.2862 mm	29.2862 mm	29.2862 mm
Humidity sensitivity level	-	3	3	3
Dedicated input times	-	2	2	2
Number of I/O lines	-	64	64	64
Number of macro cells	-	128	128	128
Number of terminals	-	84	84	84
Maximum operating temperature	-	70 °C	70 °C	70 °C
organize	-	2 DEDICATED INPUTS, 64 I/O	2 DEDICATED INPUTS, 64 I/O	2 DEDICATED INPUTS, 64 I/O
Output function	-	MACROCELL	MACROCELL	MACROCELL
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	QCCJ	QCCJ	QCCJ
Encapsulate equivalent code	-	LDCC84,1.2SQ	LDCC84,1.2SQ	LDCC84,1.2SQ
Package shape	-	SQUARE	SQUARE	SQUARE
Package form	-	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
power supply	-	5 V	5 V	5 V
Programmable logic type	-	EE PLD	EE PLD	EE PLD
propagation delay	-	15 ns	20 ns	10 ns
Certification status	-	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	4.57 mm	4.57 mm	4.57 mm
Maximum supply voltage	-	5.25 V	5.25 V	5.25 V
Minimum supply voltage	-	4.75 V	4.75 V	4.75 V
Nominal supply voltage	-	5 V	5 V	5 V
surface mount	-	YES	YES	YES
technology	-	CMOS	CMOS	CMOS
Temperature level	-	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	-	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	-	J BEND	J BEND	J BEND
Terminal pitch	-	1.27 mm	1.27 mm	1.27 mm
Terminal location	-	QUAD	QUAD	QUAD
width	-	29.2862 mm	29.2862 mm	29.2862 mm

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