MK5027
SS7 SIGNALLING
LINK CONTROLLER
CMOS
FULLY COMPATIBLE WITH BOTH 8 OR 16
BIT SYSTEMS
SYSTEM CLOCK RATE TO 10MHz. DATA
RATE UP TO 2.5Mbps FOR SS7 PROTOCOL
PROCESSING,7Mbps FOR TRANSPARENT
HDLC MODE
COMPLETE LEVEL 2 IMPLEMENTATION
COMPATIBLE WITH 1988 CCITT, AT&T,
ANSI, AND BELLCORE SIGNALLING SYS-
TEM NUMBER 7 LINK LEVEL PROTOCOLS
52 PIN PLCC AND 48-PIN DIP PIN-FOR-PIN
COMPATIBLE WITH THE SGS-THOMSON
X.25 CHIP (MK5025) AND NEARLY PIN-FOR-
PIN COMPATIBLE WITH THE SGS-THOM-
SON VLANCE CHIP (MK5032)
BUFFER MANAGEMENT INCLUDES:
- Initialization Block
- Separate Receive and Transmit Rings
- Variable Descriptor Ring and Window Sizes.
ON CHIP DMA CONTROL WITH PROGRAM-
MABLE BURST LENGTH
SELECTABLE BEC OR PCR RETRANSMIS-
SION METHODS, INCLUDING FORCED RE-
TRANSMISSION FOR PCR
HANDLES ALL 7 SS7 TIMERS
HANDLES ALL SS7 FRAME FORMATTING:
- Zero bit insert and delete
- FCS generation and detection
- Frame delimiting with flags
PROGRAMMABLE MINIMUM SIGNAL UNIT
SPACING (number of flags between SU’s)
HANDLES ALL SEQUENCING AND LINK
CONTROL
SELECTABLE FCS OF 16 OR 32 BITS.
TESTING FACILITIES:
- Internal Loopback
- Silent Loopback
- Optional Internal Data Clock Generation
- Self Test
ALL INPUTS AND OUTPUTS ARE TTL COM-
PATIBLE
PROGRAMMABLE FOR FULL OR HALF DU-
PLEX OPERATION
DESCRIPTION
The SGS-THOMSON Signalling System #7 Sig-
nalling Link Controller (MK5027) is a VLSI semi-
August 1989
DIP48
PLCC52
conductor device which provides a complete link
control function conforming to the 1988 CCITT
version of SS7. This includes frame formatting,
transparency (so called ”bit-stufling”), error recov-
ery by two types of retransmission, error monitor-
ing, sequence number control, link status con-
trol, and FISU generation. One of the outstanding
features of the MK5027 is its buffer management
which includes on-chip DMA. This feature allows
users to handlq multiple packets of receive and
transmit data at a time. (A conventional data link-
control chip plus a separate DMA chip would han-
dle data for only a single block at a time.) The
MK5027 may be used with any of several popular
16 and 8 bit microprocessors, such as 68000,
6800, Z8000, Z80, LSI-11, 8086, 8088, 8080, etc.
Figure 1:
Pin Connection.
VSS-GND
DAL07
DAL06
DAL05
DAL04
DAL03
DAL02
DAL01
DAL00
READ
INTR
DALI
DALO
DAS
BMO, BYTE, BUSREL
BMI, BUSAKO
HOLD, BUSRQ
ALE, AS
HLDA
CS
ADR
READY
RESET
VSS-GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
VCC (+5V)
DAL08
DAL09
DAL10
DAL11
DAL12
DAL13
DAL14
DAL15
A16
A17
A18
A19
A20
A21
A22
A23
RD
DSR, CTS
TD
SYSCLK
RCLK
DTR, RTS
TCLK
M
K
5
0
H
2
5
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1/19
MK5027
Table 1:
Pin Description.
LEGEND:
I
IO
OD
Input only
Input/Output
O
3S
Output only
3-State
Open Drain (no internal pull-up)
Pin(s)
2-9
40-47
Type
IO/3S
Descriplion
The time multiplexed Data Address bus. During the address portion of a
memory transfer, DALe15:00 contains the lower 16 bits of the memory
address.
During the data portion of a memory transfer, DAL<15:00> contains the
read or write data, depending on the type of transfer.
READ indicates the type of operation that the bus controller is performing
during a bus transaction. READ is driven by the MK5027 only while it is
the BUS MASTER. READ is valid during the entire bus transaction and is
tristated at all other times.
MK5027 as a Bus Slave:
READ = HIGH - Data is placed on the DAL lines by the chip.
READ = LOW - Data is taken off the DAL lines by the chip.
MK5027 as a Bus Master:
READ = HIGH - Data is taken off the DAL lines by the chip.
READ = LOW - Data is placed on the DAL lines by the chip.
INTERRUPT is an attention interrupt line that indicates that one or more of
the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT.
INTERRUPT is enabled by CSR0<0.9>, INEA = 1.
DAL IN is an external bus transceiver control line. DALI is driven by the
MK5027 only while it is the BUS MASTER. DALI is asserted by the
MK5027 when | ads from the DAL lines during the data portion of a READ
transfer. DALI is not asserted during a WRITE transfer.
DAL OUT is an external bus transceiver control line. DALO is driven by
the MK5027 only while it is the BUS MASTER. DALO is asserted by the
MK5027 when it drives the DAL lines during the address portion of a
READ transfer or for the duration of a WRITE transfer.
DATA STROBE defines the data portio,n of a transaction. By definition,
data is stable and valid at the low to high transition of DAS. This signal is
driven by the MK5027 while it is the BUS MASTER. During the BUS
SLAVE operation, this pin is used as an input. At all other times the signal
is tristated.
I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is
set to a one, pin 15 becomes input BUSREL and is used by the host to
signal the MK5027 to terminate a DMA burst after the current bus transfer
has completed. If bit 06 is clear the pin 15 is an output and behaves as
described below for pin 16.
Signal Name
DAL<15:00>
READ
10
IO/3S
INTR
11
O/OD
DALI
12
O/3S
DALO
13
O/3S
DAS
14
IO/3S
BMO
BYTE
BUSREL
15
IO/3S
Note:
Pin out shown is for 48 pin dip.
2/19
MK5027
Table 1:
Pin Description (continued)
Signal Name
BM1
BUSAKO
Pin(s)
16
Type
O/3S
Descriplion
Pins 15 and 16 are programmable though bit 00 of CSR4 (BCON).
If CSR4<00> BCON = 0,
I/O PIN 15 = BMO (O/3S)
I/O PIN 16 = BM1 (O/3S)
BYTE MASK<1:0> indicates the byte(s) on the DAL to be read or written
during this bus transaction. MK5027 drives these lines only as a Bus
Master. MK5027 ignores the BM lines when it is a Bus Slave.
Byte selection is done as outlined in the following table.
BM1
BM0
TYPE OF TRANSFER
LOW
LOW
ENTIRE WORD
LOW
HIGH
UPPER BYTE (DAL<15:08>)
HIGH
LOW
LOWER BYTE (DAL<07:00>)
HIGH
HIGH
NONE
If CSR4<00>BCON = 1,
I/O PIN 15 = BYTE (O/3S)
I/O PIN 16 = BUSAKO(O)
Byte selection is done using the BYTE line and DAL<00> latched during
the address portion of the bus transaction. MK5027 drives BYTE only a
Bus Master and ignores it when a Bus Slave. Byte selection is done as
outlined in the following table.
BYTE
LOW
LOW
HIGH
HIGH
DAL<00>
LOW
HIGH
LOW
HIGH
TYPE OF TRANSFER
ENTIRE WORD
ILLEGAL CONDITION
LOWER BYTE
UPPER BYTE
HOLD
BUSRQ
17
IO/OD
ALE
AS
18
O/3S
HLDA
19
I
BUSAKO is a bus request daisy chain output. If MK5027 is not requesting
the bus and it receives HLDA, BUSAKO will be driven low. If MK5027 is
requesting the bus when it receives HLDA, BUSAKO will remain high.
Note: All transfers are entire word unless the MK5027 is configured for 8
bit operation.
Pins 17 is configured through bit 0 of CSR4.
If CSR4<00> BCON = 0,
I/O PIN 17 = HOLD
HOLD request is asserted by MK5027 when it requires a DMA cycle, if
HLDA is inactive, regardless of the previous state of the HOLD pin.
HOLD is held low for the entire ensuing bus transaction.
If CSR4<00> BCON = 1,
I/O PIN 17 = BUSRQ
BUSRQ is asserted by MK5027 when it requires a DMA cycle if the prior
state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held
low for the entire ensuing bus transaction.
The active level of ADDRESS STROBE is programmable through CSR4.
The address portion of a bus transfer occurs while this signal is at its
asserted level. This signal is driven by MK5027 while it is the BUS
MASTER. At all other times, the signal is tristated.
If CSR4<01> ACON = 0,
I/O PIN 18 = ALE
ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define
the address portion of the transfer and remains low during the data portion.
If CSR4<01> ACON = 1,
I/O PIN 18 = AS
As AS, the signal pulses low during the address portion of the bus
transfer. The low to high transition of AS can be used by a slave device to
strobe the address into a register.
AS is effectively the inversion of ALE.
HOLD AKNOWLEDGE is the response to HOLD. When HLDA is low in response
to MK5027’s assertion of HOLD, the MK5027 is the Bus Master. HLDA should be
desasserted ONLY after HOLD has been released by the MK5027.
3/19
MK5027
Table 1:
Pin Description (continued)
Signal Name
CS
ADR
Pin(s)
20
21
Type
I
I
Descriplion
CHIP SELECT indicates, when low, that the MK5027 is the slave device
for the data transfer.CS must be valid througout the enture transaction.
ADDRESS selects the Register Address Port or the Register Data Port. It
must be valid throughout the data portion of the transfer and is only used
by the chip when CS is low.
ADR
LOW
HIGH
READY
22
IO/OD
PORT
REGISTER DATA PORT
REGISTER ADDRESS PORT
When the MK5027 is a Bus Master, READY is an asynchronous
acknowledgement from the bus memory that memory will accept data in a
WRITE cycle or that memory has put data on the DAL lines in a READ
cycle.
As a bus Slave, the MK5027 asserts READY when it has put data on the
DAL lines during a READ cycle or is about to take data from the DAL lines
during WRITE cycle. READY is a response to DAS and it will be released
after DAS or CS is negated.
RESET is the Bus signal that will cause MK5027 to cease operation, clear
its internal logic and enter an idle state with the Power Off bit of CSR0 set.
TRANSMIT CLOCK. A 1x clock input for transmitter timing. TD changes
on the falling edge of TCLK. The frequency of TCLK may not be greater
than the frequency of SYSCLK.
DATA TERMINAL READY, REQUEST TO SEND. Modem control pin. Pin
26 is configurable through CSR5. This pin can be programmed to behave
as output RTS or as programmable IO pin DTR. If configured as RTS, the
MK5027 will assert this pin if it has data to send and throughout the
transmission of a signal unit.
RECEIVE CLOCK. A 1x clock input for receiver timing. RD is sampled on
the rising edge of RCLK. The frequency of RCLK may not be greater than
the frequency of SYSCLK.
SYSTEM CLOCK. System clock used for internal timing of the MK5027.
SYSCLK should be a square wave, of frequency up to 10MHz.
TRANSMIT DATA. Transmit serial data output.
DATA SET READY, CLEAR TO SEND. Modem Control Pin. Pin 30 is
configurable through CSR5. This pin can be programmed to behave as
input CTS or as programmable IO pin DSR. If configured as CTS, the
MK5027 will transmit all ones while CTS is high.
RECEIVE DATA. Received serial data input.
Address bits <23:16> used in conjunction with DAL <15:00> to produce a
24 bit address. MK5027 drives these lines only as a Bus Master.
A23-A20 may be driven continuously as described in the CSR4<7> BAEN
bit.
Ground Pins
Power Supply Pin
+5.0 VDC
±
5%
RESET
TCLK
23
25
I
I
DTR
RTS
26
IO
RCLK
27
I
SYSCLK
TD
DSR
CTS
28
29
30
I
O
IO
RD
A<23:16>
31
32-39
I
O/3S
VSS-GND
VCC
1, 24
48
4/19
MK5027
Figure 2:
Possible System Configuration for the MK5027.
5/19
PCB Design
京公网安备 11010802033920号
EEWORLD
