HD-6409
March 1997
CMOS Manchester Encoder-Decoder
Description
The HD-6409 Manchester Encoder-Decoder (MED) is a high
speed, low power device manufactured using self-aligned sil-
icon gate technology. The device is intended for use in serial
data communication, and can be operated in either of two
modes. In the converter mode, the MED converts Non
return-to-Zero code (NRZ) into Manchester code and
decodes Manchester code into Nonreturn-to-Zero code. For
serial data communication, Manchester code does not have
some of the deficiencies inherent in Nonreturn-to-Zero code.
For instance, use of the MED on a serial line eliminates DC
components, provides clock recovery, and gives a relatively
high degree of noise immunity. Because the MED converts
the most commonly used code (NRZ) to Manchester code,
the advantages of using Manchester code are easily realized
in a serial data link.
In the Repeater mode, the MED accepts Manchester code
input and reconstructs it with a recovered clock. This mini-
mizes the effects of noise on a serial data link. A digital
phase lock loop generates the recovered clock. A maximum
data rate of 1MHz requires only 50mW of power.
Manchester code is used in magnetic tape recording and in
fiber optic communication, and generally is used where data
accuracy is imperative. Because it frames blocks of data, the
HD-6409 easily interfaces to protocol controllers.
Features
• Converter or Repeater Mode
• Independent Manchester Encoder and Decoder
Operation
• Static to One Megabit/sec Data Rate Guaranteed
• Low Bit Error Rate
• Digital PLL Clock Recovery
• On Chip Oscillator
• Low Operating Power: 50mW Typical at +5V
• Available in 20 Lead Dual-In-Line and 20 Pad LCC
Package
Ordering Information
PACKAGE
PDIP
SOIC
CERDIP
DESC
CLCC
DESC
TEMPERATURE
RANGE
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-55
o
C to 125
o
C
-40
o
C to +85
o
C
-55
o
C to 125
o
C
1 MEGABIT/SEC
HD3-6409-9
HD9P6409-9
HD1-6409-9
5962-9088801MRA
HD4-6409-9
5962-9088801M2A
PKG.
NO.
E20.3
M20.3
F20.3
F20.3
J20.A
J20.A
Pinouts
HD-6409 (CERDIP, PDIP, SOIC)
TOP VIEW
HD-6409 (CLCC)
TOP VIEW
BOO
19
18 BZO
17 SS
16 ECLK
15 CTS
14 MS
9
RST
10
GND
11
CO
12
IX
13
OX
BZI
BOI
UDI
SD/CDS
SDO
SRST
NVM
DCLK
RST
1
2
3
4
5
6
7
8
9
20 V
CC
19 BOO
18 BZO
17 SS
16 ECLK
15 CTS
14 MS
13 OX
12 IX
11 CO
NVM
DCLK
7
8
SD/CDS
SDO
SRST
4
5
6
3
2
1
20
GND 10
V
CC
BOI
UDI
BZI
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
2951.1
5-1
HD-6409
Block Diagram
SDO
NVM
BOI
BZI
UDI
EDGE
DETECTOR
RST
SD/CDS
RESET
SD
INPUT/
OUTPUT
SELECT
MANCHESTER
ENCODER
COMMAND
SYNC
GENERATOR
CTS
DATA
INPUT
LOGIC
5-BIT SHIFT
REGISTER
AND DECODER
OUTPUT
SELECT
LOGIC
BOO
BZO
SRST
MS
IX
OX
CO
SS
OSCILLATOR
ECLK
DCLK
COUNTER
CIRCUITS
Logic Symbol
SS
CO
17
11
13
CLOCK
GENERATOR
12
OX
IX
SD/CDS
ECLK
4
16
ENCODER
19
18
15
BOO
BZO
CTS
MS
RST
SDO
DCLK
NVM
SRST
14
9
5
8
7
6
CONTROL
2
1
3
BOI
BZI
UDI
DECODER
5-2
HD-6409
Pin Description
PIN
NUMBER
1
TYPE
I
SYMBOL
BZl
NAME
Bipolar Zero Input
DESCRIPTION
Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II
encoded data to the decoder, BZI and BOl are logical complements. When using
pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high.
Used in conjunction with pin 1, Bipolar Zero Input (BZI), to input Manchester II
encoded data to the decoder, BOI and BZI are logical complements. When using
pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low.
An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) is used to input
Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2
(BOl) for data input, UDI must be held low.
In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ
data is accepted synchronously on the falling edge of encoder clock output
(ECLK). In the repeater mode, SD/CDS is an output indicating the status of last
valid sync pattern received. A high indicates a command sync and a low indicates
a data sync pattern.
The decoded serial NRZ data is transmitted out synchronously with the decoder
clock (DCLK). SDO is forced low when RST is low.
In the converter mode, SRST follows RST. In the repeater mode, when RST goes
low, SRST goes low and remains low after RST goes high. SRST goes high only
when RST is high, the reset bit is zero, and a valid synchronization sequence is
received.
A low on NVM indicates that the decoder has received invalid Manchester data
and present data on Serial Data Out (SDO) is invalid. A high indicates that the
sync pulse and data were valid and SDO is valid. NVM is set low by a low on RST,
and remains low after RST goes high until valid sync pulse followed by two valid
Manchester bits is received.
The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchro-
nously output received NRZ data (SDO).
In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low.
A high on RST enables SDO and DCLK, and forces SRST high. NVM remains
low after RST goes high until a valid sync pulse followed by two Manchester bits
is received, after which it goes high. In the repeater mode, RST has the same ef-
fect on SDO, DCLK and NVM as in the converter mode. When RST goes low,
SRST goes low and remains low after RST goes high. SRST goes high only
when RST is high, the reset bit is zero and a valid synchronization sequence is
received.
Ground
Buffered output of clock input I
X
. May be used as clock signal for other peripherals.
I
X
is the input for an external clock or, if the internal oscillator is used, I
X
and O
X
are used for the connection of the crystal.
If the internal oscillator is used, O
X
and I
X
are used for the connection of the crys-
tal.
MS must be held low for operation in the converter mode, and high for operation
in the repeater mode.
In the converter mode, a high disables the encoder, forcing outputs BOO, BZO high
and ECLK low. A high to low transition of CTS initiates transmission of a Command
sync pulse. A low on CTS enables BOO, BZO, and ECLK. In the repeater mode,
the function of CTS is identical to that of the converter mode with the exception that
a transition of CTS does not initiate a synchronization sequence.
In the converter mode, ECLK is a 1X clock output used to receive serial NRZ data
to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from
BZl and BOl data by the digital phase locked loop.
2
I
BOl
Bipolar One Input
3
I
UDI
Unipolar Data Input
4
I/O
SD/CDS
Serial Data/Com-
mand Data Sync
5
6
O
O
SDO
SRST
Serial Data Out
Serial Reset
7
O
NVM
Nonvalid Manchester
8
9
O
I
DCLK
RST
Decoder Clock
Reset
10
11
12
13
14
15
I
O
I
O
I
I
GND
C
O
I
X
O
X
MS
CTS
Ground
Clock Output
Clock Input
Clock Drive
Mode Select
Clear to Send
16
O
ECLK
Encoder Clock
5-3
HD-6409
Pin Description
PIN
NUMBER
17
18
19
20
NOTE: (I) Input
TYPE
I
O
O
I
SYMBOL
SS
BZO
BOO
V
CC
(O) Output
NAME
Speed Select
Bipolar Zero Output
Bipolar One Out
V
CC
DESCRIPTION
A logic high on SS sets the data rate at 1/32 times the clock frequency while a
low sets the data rate at 1/16 times the clock frequency.
BZO and its logical complement BOO are the Manchester data outputs of the en-
coder. The inactive state for these outputs is in the high state.
See pin 18.
V
CC
is the +5V power supply pin. A 0.1µF decoupling capacitor from V
CC
(pin-
20) to GND (pin-10) is recommended.
Encoder Operation
The encoder uses free running clocks at 1X and 2X the data
rate derived from the system clock l
X
for internal timing. CTS
is used to control the encoder outputs, ECLK, BOO and
BZO. A free running 1X ECLK is transmitted out of the
encoder to drive the external circuits which supply the NRZ
data to the MED at pin SD/CDS.
A low on CTS enables encoder outputs ECLK, BOO and
BZO, while a high on CTS forces BZO, BOO high and holds
ECLK low. When CTS goes from high to low
1
, a synchro-
nization sequence is transmitted out on BOO and BZO. A
synchronization sequence consists of eight Manchester “0”
CTS
1
ECLK
bits followed by a command sync pulse.
2
A command
sync pulse is a 3-bit wide pulse with the first 1 1/2 bits high
followed by 1 1/2 bits low.
3
Serial NRZ data is clocked into
the encoder at SD/CDS on the high to low transition of ECLK
during the command sync pulse. The NRZ data received is
encoded into Manchester II data and transmitted out on
BOO and BZO following the command sync pulse.
4
Fol-
lowing the synchronization sequence, input data is encoded
and transmitted out continuously without parity check or
word framing. The length of the data block encoded is
defined by CTS. Manchester data out is inverted.
SD/CDS
‘1’
BZO
‘1’
BOO
‘0’ ‘1’
2 0
0
0
‘0’
‘1’
DON’T CARE
0
0
0
0
0 3
4
EIGHT “0’s”
COMMAND
SYNC
SYNCHRONIZATION SEQUENCE
t
CE6
t
CE5
FIGURE 1. ENCODER OPERATION
Decoder Operation
The decoder requires a single clock with a frequency 16X or
32X the desired data rate. The rate is selected on the speed
select with SS low producing a 16X clock and high a 32X
clock. For long data links the 32X mode should be used as
this permits a wider timing jitter margin. The internal opera-
tion of the decoder utilizes a free running clock synchronized
with incoming data for its clocking.
The Manchester II encoded data can be presented to the
decoder in either of two ways. The Bipolar One and Bipolar
Zero inputs will accept data from differential inputs such as a
comparator sensed transformer coupled bus. The Unipolar
Data input can only accept noninverted Manchester II
encoded data i.e. Bipolar One Out through an inverter to
Unipolar Data Input. The decoder continuously monitors this
data input for valid sync pattern. Note that while the MED
encoder section can generate only a command sync pattern,
the decoder can recognize either a command or data sync
pattern. A data sync is a logically inverted command sync.
5-4
HD-6409
There is a three bit delay between UDI, BOl, or BZI input and
the decoded NRZ data transmitted out of SDO.
Control of the decoder outputs is provided by the RST pin.
When RST is low, SDO, DCLK and NVM are forced low.
When RST is high, SDO is transmitted out synchronously
with the recovered clock DCLK. The NVM output remains
low after a low to high transition on RST until a valid sync
pattern is received.
DCLK
The decoded data at SDO is in NRZ format. DCLK is pro-
vided so that the decoded bits can be shifted into an external
register on every high to low transition of this clock. Three bit
periods after an invalid Manchester bit is received on UDI, or
BOl, NVM goes low synchronously with the questionable
data output on SDO. FURTHER, THE DECODER DOES
NOT REESTABLISH PROPER DATA DECODING UNTIL
ANOTHER SYNC PATTERN IS RECOGNIZED.
UDI
COMMAND
SYNC
SDO
1
0
0
1
0
1
0
1
0
1
0
1
0
RST
NVM
FIGURE 2. DECODER OPERATION
Repeater Operation
Manchester Il data can be presented to the repeater in either
of two ways. The inputs Bipolar One In and Bipolar Zero In
will accept data from differential inputs such as a comparator
or sensed transformer coupled bus. The input Unipolar Data
In accepts only noninverted Manchester II coded data. The
decoder requires a single clock with a frequency 16X or 32X
the desired data rate. This clock is selected to 16X with
Speed Select low and 32X with Speed Select high. For long
data links the 32X mode should be used as this permits a
wider timing jitter margin.
The inputs UDl, or BOl, BZl are delayed approximately 1/2
bit period and repeated as outputs BOO and BZO. The 2X
ECLK is transmitted out of the repeater synchronously with
BOO and BZO.
INPUT
COUNT
ECLK
SYNC PULSE
UDI
1
2
3
A low on CTS enables ECLK, BOO, and BZO. In contrast to
the converter mode, a transition on CTS does not initiate a
synchronization sequence of eight 0’s and a command sync.
The repeater mode does recognize a command or data sync
pulse. SD/CDS is an output which reflects the state of the
most recent sync pulse received, with high indicating a com-
mand sync and low indicating a data sync.
When RST is low, the outputs SDO, DCLK, and NVM are
low, and SRST is set low. SRST remains low after RST goes
high and is not reset until a sync pulse and two valid
manchester bits are received with the reset bit low. The reset
bit is the first data bit after the sync pulse. With RST high,
NRZ Data is transmitted out of Serial Data Out synchro-
nously with the 1X DCLK.
4
5
6
7
BZO
BOO
RST
SRST
FIGURE 3. REPEATER OPERATION
5-5
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