• Wide power supply operating range from 3.0V to 5.5V
• Available QML Q or V processes
• 14-lead flatpack
• UT54ACTS74E-SMD- 5962-96535
DESCRIPTION
The UT54ACTS74E contains two independent D-type positive
triggered flip-flops. A low level at the Preset or Clear inputs
sets or resets the outputs regardless of the levels of the other
inputs. When Preset and Clear are inactive (high), data at the
D input meeting the setup time requirement is transferred to the
outputs on the positive-going edge of the clock pulse. Follow-
ing the hold time interval, data at the D input may be changed
without affecting the levels at the outputs.
The device is characterized over full HiRel temperature range
of -55C to +125C.
FUNCTION TABLE
INPUTS
PRE
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
L
D
X
X
X
H
L
X
OUTPUT
Q
H
L
H
1
H
L
Q
o
Q
L
H
H
1
L
H
Q
o
14-Lead Flatpack
TopView
CLR1
D1
CLK1
PRE1
Q1
Q1
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
CLR2
D2
CLK2
PRE2
Q2
Q2
LOGIC SYMBOL
PRE1
CLK1
D1
CLR1
PRE2
CLK2
D2
CLR2
(4)
(3)
(2)
(1)
(10)
(11)
(12)
(13)
(9)
(8)
Q2
Q2
S
C1
D1
R
(5)
(6)
Q1
Q1
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
Note:
1. The output levels in this configuration are not guaranteed to meet the mini-
mum levels for V
OH
if the lows at preset and clear are near V
IL
maximum.
In addition, this configuration is nonstable; that is, it will not persist when
either preset or clear returns to its inactive (high) level.
1
LOGIC DIAGRAM
PRE
CLR
Q
CLK
Q
D
2
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
JC
I
I
P
D2
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum package power dissipation
permitted @ T
C
= +125
o
C
LIMIT
-0.3 to 7.0
-0.3 to V
DD
+0.3
-65 to +150
+175
+300
15.5
10
3.2
UNITS
V
V
C
C
C
C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these
or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
2. Per MIL-STD-883, method 1012.1, Section 3.4.1, P
D
= (T
J(max)
- T
C(max)
) /
JC
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
3.0 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
C
3
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS74E
7
( V
DD
= 3.0V to 5.5V; V
SS
= 0V
6
; -55C < T
C
< +125C)
SYMBOL
V
IL1
V
IL2
V
IH1
V
IH2
I
IN
V
OL1
DESCRIPTION
Low-level input voltage
1
Low-level input voltage
1
High-level input voltage
1
High-level input voltage
1
Input leakage current
Low-level output voltage
3
CONDITION
V
DD
from 4.5V to 5.5V
V
DD
from 3.0V to 3.6V
V
DD
from 4.5V to 5.5V
V
DD
from 3.0V to 3.6V
V
IN
= V
DD
or V
SS
I
OL
= 8ma
V
DD
= 4.5V to 5.5V
V
OL2
Low-level output voltage
3
I
OL
= 6ma
V
DD
= 3.0V to 3.6V
V
OH1
High-level output voltage
3
I
OH
= -8ma
V
DD
from 4.5V to 5.5V
V
OH2
High-level output voltage
3
I
OH
= -6ma
V
DD
from 3.0V to 3.6V
I
OS1
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS
V
DD
from 4.5V to 5.5V
I
OS2
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS
V
DD
from 3.0V to 3.6V
I
OL1
Low level output current
9
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 4.5V to 5.5V
I
OL2
Low level output current
9
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 3.0V to 3.6V
I
OH1
High level output current
9
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 4.5V to 5.5V
I
OH2
High level output current
9
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 3.0V to 3.6V
-6
mA
-8
mA
6
mA
8
mA
-100
100
mA
-200
200
mA
2.4
V
0.7 V
DD
V
0.4
V
0.5 V
DD
2.0
-1
1
0.4
MIN
MAX
0.8
0.8
UNIT
V
V
V
V
A
V
4
P
total1
Power dissipation
2, 8
C
L
= 50pF
V
DD
= 4.5V to 5.5V
1.0
mW/
MHz
mW/
MHz
A
P
total2
Power dissipation
2, 8
C
L
= 50pF
V
DD
= 3.0V to 3.6V
0.5
I
DDQ
I
DDQ
Quiescent Supply Current
V
IN
= V
DD
or V
SS
V
DD
from 3.0V to 5.5V
10
Quiescent Supply Current Delta
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
= 1MHz
V
DD
= 0V
= 1MHz
V
DD
= 0V
1.6
mA
C
IN
Input capacitance
5
Output capacitance
5
15
pF
C
OUT
15
pF
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
5.0E5
amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
1E6 rads(Si) per MIL-STD-883 Method 1019.
8. Power dissipation specified per switching output.
9. Guaranteed by characterization, but not tested.
京公网安备 11010802033920号
EEWORLD
