EEWORLDEEWORLDEEWORLD

Part Number

Search

8N4QV01KG-0048CD8

Description
LVDS Output Clock Oscillator
CategoryPassive components    oscillator   
File Size185KB,19 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

8N4QV01KG-0048CD8 Overview

LVDS Output Clock Oscillator

8N4QV01KG-0048CD8 Parametric

Parameter NameAttribute value
MakerIDT (Integrated Device Technology)
Reach Compliance Codecompliant
Oscillator typeLVDS
Base Number Matches1
Quad-Frequency Programmable
VCXO
IDT8N4QV01 REV G
DATA SHEET
General Description
The IDT8N4QV01 is a Quad-Frequency Programmable VCXO with
very flexible frequency and pull-range programming capabilities.
The device uses IDT’s fourth generation FemtoClock® NG
technology for an optimum of high clock frequency and low phase
noise performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 10-lead ceramic 5mm x
7mm x 1.55mm package.
Besides the 4 default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N4QV01 can be programmed via the I
2
C
interface to any output clock frequency between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷N (N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to 4
independent PLL, P, M and N divider registers (P, MINT, MFRAC
and N), reprogramming those registers to other frequencies under
control of FSEL0 and FSEL1 is supported. The extended
temperature range supports wireless infrastructure, tele-
communication and networking end equipment requirements.
Features
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Four power-up default frequencies (see part number order
codes), re-programmable by I
2
C
I
2
C programming interface for the output clock frequency, APR
and internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
Absolute pull-range (APR) programmable from ±4.5ppm to
±754.5ppm
One 2.5V or 3.3V LVDS differential clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.494ps
(typical)
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.594ps
(typical)
2.5V or 3.3V supply voltage modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Block Diagram
OSC
114.285 MHz
÷MINT,
MFRAC
2
VC
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pin Assignment
÷P
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Q
nQ
VC 1
OE 2
GND 3
FSEL0 4
FSEL1 5
10 SCLK
9 SDATA
8 V
DD
7 nQ
6 Q
A/D
7
25
Configuration Register (ROM)
(Frequency, APR, Polarity)
I
2
C Control
7
IDT8N4QV01 REV G DATA SHEET
10-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
IDT8N4QV01GCD
FEBRUARY 24, 2012
1
©2012 Integrated Device Technology, Inc.
I'm changing jobs soon, looking for advice
I am about to change jobs. Currently, there are two companies for me to choose from. One is for WINCE drivers, and the other is for LINUX drivers. I have worked on both systems and am more familiar wi...
lbf_78 Embedded System
Design of Position Loop and Electronic Gear in Fully Digital Servo System
Abstract: The working principle of the position loop and electronic gear in the servo system is analyzed, and a digital implementation method of the position loop and electronic gear is introduced. Fi...
zbz0529 Power technology
[Book Recommendation] Programming Forum: C language core development technology from entry to mastery.pdf
Introduction "Programming Forum: C Language Core Development Technology from Entry to Mastery" explains C language development technology from the simplest to the most advanced, with a scientific and ...
qinkaiabc Programming Basics
Choosing the ADC Architecture That Best Fits Your Application Needs Part 2: Precision SAR and Delta Sigma Analog-to-Digital Converters
[align=left][font=宋体][size=11.0pt]The animated short film will introduce the working principle of the successive approximation register (SAR) [/size][/font][size=11.0pt] ADC [/size][font=宋体][size=11.0...
德州仪器_视频 Analogue and Mixed Signal
I would like to ask about the issue of nor flash erasing/
I would like to ask how to erase only a few bytes in a sector when the nor flash can only be erased with setor...
weiyt Embedded System
『Brand new』 Tianqian TQ210 Cortex-A8 development board transfer full set plus 7-inch LCD, within the warranty period
[i=s] This post was last edited by qinqincaoyuan on 2016-4-15 20:28 [/i] I was too greedy at the time. I had just learned 51 single-chip microcomputers for a few days, but I wanted to learn stm32 and ...
qinqin草原 Buy&Sell

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1831  1445  833  455  1538  37  30  17  10  31 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号