Integrated
Circuit
Systems, Inc.
ICS9FG104
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA Clocks
Recommended Application:
Pin Configuration
Frequency Timing Generator for Differential CPU & SATA clocks
XIN/CLKIN 1
Features:
•
Generates common CPU frequencies from 14.318 MHz
or 25 MHz
•
Crystal or reference input
•
4 - 0.7V current-mode differential output pairs
•
Supports Serial-ATA at 100 MHz
•
Two spread spectrum modes: 0 to -0.5 downspread and
+/-0.25% centerspread
•
Unused inputs may be disabled in either driven or Hi-Z
state for power management.
•
M/N Programming
Key Specifications:
•
Output cycle-to-cycle jitter < 50 ps
•
Output to output skew < 35 ps
•
+/-300 ppm frequency accuracy on output clocks
X2
VDD
GND
REFOUT
FS2
DIF_3
DIF_3#
VDD
GND
DIF_2
DIF_2#
SDATA
SCLK
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
FS0
FS1
DIF_0
DIF_0#
VDD
GND
DIF_1
DIF_1#
SEL14M_25M#
SPREAD
DIF_STOP#
28-pin SSOP/TSSOP
Frequency Select Table
SEL14M_25M#
FS2 FS1 FS0 OUTPUT(MHz)
(FS3)
0
0
0
0
100.00
0
0
0
1
125.00
0
0
1
0
133.33
0
0
1
1
166.67
0
1
0
0
200.00
0
1
0
1
266.00
0
1
1
0
333.00
0
1
1
1
400.00
1
0
0
0
100.00
1
0
0
1
125.00
1
0
1
0
133.33
1
0
1
1
166.67
1
1
0
0
200.00
1
1
0
1
266.00
1
1
1
0
333.00
1
1
1
1
400.00
0839D—06/02/05
ICS9FG104
Integrated
Circuit
Systems, Inc.
ICS9FG104
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
XIN/CLKIN
X2
VDD
GND
REFOUT
FS2
DIF_3
DIF_3#
VDD
GND
DIF_2
DIF_2#
SDATA
SCLK
DIF_STOP#
SPREAD
SEL14M_25M#
DIF_1#
DIF_1
GND
VDD
DIF_0#
DIF_0
FS1
FS0
IREF
GNDA
VDDA
PIN TYPE
IN
OUT
PWR
IN
IN
IN
IN
OUT
PWR
PWR
OUT
OUT
I/O
IN
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
PWR
PWR
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Reference Clock output
Frequency select pin.
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock outputs
0.7V differential complement clock outputs
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Active low input to stop differential output clocks.
Asynchronous, active high input, with internal 120Kohm pull-up resistor,
to enable spread spectrum functionality.
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 =
25 MHz
0.7V differential complement clock outputs
0.7V differential true clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock outputs
0.7V differential true clock outputs
Frequency select pin.
Frequency select pin.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
0839D—06/02/05
2
Integrated
Circuit
Systems, Inc.
ICS9FG104
General Description
The
ICS9FG104
is a Frequency Timing Generator that provides 4 differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express and SATA. The part synthesizes several output frequencies from either
a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It
provides outputs with cycle-to-cycle jitter of less than 50 ps and output-to-output skew of less than 35 ps.
The
ICS9FG104
also provides a copy of the reference clock. Frequency selection can be accomplished via strap pins or
SMBus control.
Block Diagram
XIN/CLKIN
OSC
X2
2
R EF OU T
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
4
DIF(3:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
SDATA
SCLK
CONTROL
LOGIC
IREF
Power Groups
Pin Number
VDD
GND
3
4
9,21
10,20
28
27
Description
REFOUT, Digital Inputs
DIF Outputs
IREF, Analog VDD, GND for PLL Core
0839D—06/02/05
3
Integrated
Circuit
Systems, Inc.
ICS9FG104
Absolute Max
Symbol
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
0
Max
V
DD
+ 0.5V
V
DD
+ 0.5V
150
70
115
Units
V
V
°
C
°C
°C
V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
V
IH
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
CONDITIONS
MIN
3.3 V +/-5%
2
V
SS
- 0.3
3.3 V +/-5%
V
IN
= V
DD
-5
V
IN
= 0 V; Inputs with no pull-up
-5
resistors
V
IN
= 0 V; Inputs with pull-up
-200
resistors
Full Active, C
L
= Full load;
f = 400 MHz
Full Active, C
L
= Full load;
f = 100 MHz
All outputs stopped driven
All outputs stopped Hi-Z
V
DD
= 3.3 V
14
Logic Inputs
Output pin capacitance
From V
DD
Power-Up and after
input clock stabilization to 1st
clock
Triangular Modulation
DIF output enable after
DIF_Stop# de-assertion
20% to 80% of VDD
1.5
TYP
UNITS NOTES
V
DD
+ 0.3
V
1
0.8
V
1
5
uA
1
uA
uA
125
110
106
48
150
125
120
60
25
7
5
6
1.8
30
33
15
5
mA
mA
mA
mA
MHz
nH
pF
pF
ms
kHz
ns
ns
1
1
1
1
1
1
3
1
1
1
1,2
1
1
1
MAX
I
DD3.3OP
Operating Supply Current
I
DD3.3STOP
Input Frequency
3
Pin Inductance
1
Input/Output
Capacitance
1
Clk Stabilization
1,2
Modulation Frequency
DIF output enable
Input Rise and Fall times
1
2
F
i
L
pin
C
IN
C
OUT
T
STAB
f
MOD
t
DIFOE
t
R
/t
F
Guaranteed by design, not 100% tested in production.
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to
meet
0839D—06/02/05
4
Integrated
Circuit
Systems, Inc.
ICS9FG104
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2Ω, R
P
=49.9Ω,
Ι
REF
= 475Ω
PARAMETER
Output Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
SYMBOL
Zo
1
CONDITIONS
V
O
= V
x
Statistical measurement on single
ended signal using oscilloscope
math function.
Measurement on single ended
signal using absolute value.
Crossing variation over all edges
see Tperiod min-max values
400MHz nominal
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
V
OL
= 0.175V, V
OH
= 0.525V
V
OH
= 0.525V V
OL
= 0.175V
MIN
3000
660
-150
-300
250
TYP
MAX
850
UNITS
Ω
mV
NOTES
1
1
1
VHigh
VLow
Vovs
Vuds
Vcross(abs)
d-Vcross
ppm
150
1150
550
140
mV
mV
mV
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
%
ps
ps
ps
ps
1
1
1
1
1,2
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
4
4
4
1
Average period
Tperiod
Absolute min period
T
absmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
Skew, output to output
Jitter, PCI-e SRC phase
Jitter, PCI-e SRC phase
Jitter, Cycle to cycle
1
2
t
r
t
f
d-t
r
d-t
f
d
t3
t
sk3
t
jPCI-ephase14
t
jPCI-ephase25
t
jcyc-cyc
-300
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
175
300
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
Measured Differentially
V
T
= 50%
22MHz/1.5MHz/1.5MHz/10ns,
14.31818 MHz REF Clock
22MHz/1.5MHz/1.5MHz/10ns,
25 MHz REF Clock
Measured Differentially
45
700
700
125
125
55
35
42
39
50
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
or 25 MHz
3
4
Figures are for down spread.
This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit
http://www.pcisig.com for additional details
0839D—06/02/05
5
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