Integrated
Circuit
Systems, Inc.
ICS854054
4:1
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
M
ULTIPLEXER
F
EATURES
•
High speed 4:1 differential multiplexer
•
One differential LVDS output
•
Four selectable differential clock inputs
•
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•
Maximum output frequency: 2.8GHz
•
Translates any single ended input signal to
LVDS levels with resistor bias on nPCLKx input
•
Part-to-part skew: 375ps (maximum)
•
Propagation delay: 700ps (maximum)
•
Supply voltage range: 3.135V to 3.465V
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS854054 is a 4:1 Differential-to-LVDS Clock
Multiplexer which can operate up to 2.8GHz and
HiPerClockS™
is a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS854054 has 4 selectable differential clock
inputs. The PCLK, nPCLK input pairs can accept LVPECL,
LVDS, CML or SSTL levels. The fully differential architec-
ture and low propagation delay make it ideal for use in clock
distribution circuits. The select pins have internal pulldown
resistors. The SEL1 pin is the most significant bit and the
binary number applied to the select pins will select the same
numbered data input (i.e., 00 selects PCLK0, nPCLK0).
IC
S
B
LOCK
D
IAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
P
IN
A
SSIGNMENT
PCLK0
nPCLK0
PCLK1
nPCLK1
V
DD
SEL0
SEL1
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Q
nQ
GND
nPCLK3
PCLK3
nPCLK2
PCLK2
00
(default)
01
Q
nQ
10
ICS854054
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
11
SEL1
SEL0
854054AG
www.icst.com/products/hiperclocks.html
1
REV. A MARCH 29, 2006
Integrated
Circuit
Systems, Inc.
ICS854054
4:1
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
M
ULTIPLEXER
Type
Input
Input
Input
Input
Power
Input
Power
Input
Input
Input
Input
Output
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Description
Non-inver ting differential clock input.
Inver ting differential clock input.
V
DD
/2 default when left floating.
Non-inver ting differential clock input.
Inver ting differential clock input.
V
DD
/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
Power supply ground.
Non-inver ting differential clock input.
Inver ting differential clock input.
V
DD
/2 default when left floating.
Non-inver ting differential clock input.
Inver ting differential clock input.
V
DD
/2 default when left floating.
Differential output pair. LVDS interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5, 16
6, 7
8, 13
9
10
11
12
14, 15
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V
DD
SEL0, SEL1
GND
PCLK2
nPCLK2
PCLK3
nPCLK3
nQ0, Q0
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
VDD/2
Parameter
Pulldown Resistor
Pullup/Pulldown Resistors
Test Conditions
Minimum Typical
75
50
Maximum
Units
kΩ
kΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL1
0
0
1
1
SEL0
0
1
0
1
Q
PCLK0
PCLK1
PCLK2
PCLK3
Outputs
nQ
nPCLK0
nPCLK1
nPCLK2
nPCLK3
854054AG
www.icst.com/products/hiperclocks.html
2
REV. A MARCH 29, 2006
Integrated
Circuit
Systems, Inc.
ICS854054
4:1
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
M
ULTIPLEXER
5.5V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
90
Units
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-10
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
I
IH
I
IL
V
PP
Input High Current
Input Low Current
PCLK0:PCLK3
nPCLK0:nPCLK3
PCLK0:PCLK3
nPCLK0:nPCLK3
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-10
-150
0.15
1.2
V
DD
Minimum
Typical
Maximum
15 0
15 0
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
1.2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx or nPCLKx is V
DD
+ 0.3V.
854054AG
www.icst.com/products/hiperclocks.html
3
REV. A MARCH 29, 2006
Integrated
Circuit
Systems, Inc.
ICS854054
4:1
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
M
ULTIPLEXER
Test Conditions
Minimum
250
1.125
Typical
450
1.25
Maximum
525
50
1.375
50
Units
mV
mV
V
mV
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.135V
TO
3.465V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
t
jit
t
sk(pp)
t
sk(i)
t
R
/ t
F
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Par t-to-Par t Skew; NOTE 2, 3
Input Skew
Output Rise/Fall Time
325
155.52 MHz,
(12kHz - 20MHz)
0.195
375
90
250
Test Conditions
Minimum
Typical
Maximum
2.8
700
Units
GHz
ps
ps
ps
ps
ps
dB
20% to 80%
50
155.52MHz,
MUX
ISOLATION
MUX Isolation
-50
Input Peak-to-Peak = 800mV
All parameters measured up to 1.5MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
854054AG
www.icst.com/products/hiperclocks.html
4
REV. A MARCH 29, 2006
Integrated
Circuit
Systems, Inc.
ICS854054
4:1
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
M
ULTIPLEXER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
-60
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter, RMS
@ 155.52MHz (12kHz - 20MHz) = <0.195ps typical
SSB P
HASE
N
OISE
dBc/H
Z
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
854054AG
www.icst.com/products/hiperclocks.html
5
REV. A MARCH 29, 2006
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