54F 74F164A Serial-In Parallel-Out Shift Register
January 1995
54F 74F164A
Serial-In Parallel-Out Shift Register
General Description
The ’F164A is a high-speed 8-bit serial-in parallel-out shift
register Serial data is entered through a 2-input AND gate
synchronous with the LOW-to-HIGH transition of the clock
The device features an asynchronous Master Reset which
clears the register setting all outputs LOW independent of
the clock The ’F164A is a faster version of the ’F164
Features
Y
Y
Y
Y
Y
Y
Typical shift frequency of 90 MHz
Asynchronous Master Reset
Gated serial data input
Fully synchronous data transfers
Guaranteed 4000V min ESD protection
’F164A is a faster version of the ’F164
Commercial
74F164APC
Military
Package
Number
N14A
Package Description
14-Lead (0 300 Wide) Molded Dual-In-Line
14-Lead Ceramic Dual-In-Line
14-Lead (0 150 Wide) Molded Small Outline JEDEC
14-Lead (0 300 Wide) Molded Small Outline EIAJ
14-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F164ADM (Note 2)
74F164ASC (Note 1)
74F164ASJ (Note 1)
74F164AFM (Note 2)
74F164ALM (Note 2)
J14A
M14A
M14D
W14B
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX and SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 10613 – 1
TL F 10613 – 4
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 10613
RRD-B30M75 Printed in U S A
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 10613 –2
TL F 10613 – 3
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
10 10
10 10
10 10
50 33 3
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
b
1 mA 20 mA
A B
CP
MR
Q
0
–Q
7
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
Functional Description
The ’F164A is an edge-triggered 8-bit shift register with seri-
al data entry and an output from each of the eight stages
Data is entered serially through one of two inputs (A or B)
either of these inputs can be used as an active HIGH En-
able for data entry through the other input An unused input
must be tied HIGH
Each LOW-to-HIGH transition on the Clock (CP) input shifts
data one place to the right and enters into Q
0
the logical
AND of the two data inputs (A
B) that existed before the
rising clock edge A LOW level on the Master Reset (MR)
input overrides all other inputs and clears the register asyn-
chronously forcing all Q outputs LOW
Mode Select Table
Operating
Mode
Reset (Clear)
Inputs
MR
L
H
H
H
H
A
X
l
l
h
h
B
X
l
h
l
h
Q
0
L
L
L
L
H
Outputs
Q
1
–Q
7
L-L
q
0
–q
6
q
0
–q
6
q
0
–q
6
q
0
–q
6
Shift
H(h)
e
HIGH Voltage Levels
L(l)
e
LOW Voltage Levels
X
e
Immaterial
q
n
e
Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition
Logic Diagram
TL F 10613 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
b
65 C to
a
150 C
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
30 mA to
a
5 0 mA
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
b
0 5V to V
CC
Standard Output
b
0 5V to
a
5 5V
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
b
60
54F 74F
Typ
Max
Units
V
08
b
1 2
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
20
V
V
V
Min
Min
I
IN
e b
18 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OL
e
20 mA
I
OL
e
20 mA
V
IN
e
2 7V
V
IN
e
7 0V
V
OUT
e
V
CC
I
ID
e
1 9
mA
All other pins grounded
V
IOD
e
150 mV
All other pins grounded
V
IN
e
0 5V
V
OUT
e
0V
CP
e
HIGH
MR
e
GND A B
e
GND
54F 10% V
CC
74F 10% V
CC
74F 5% V
CC
54F 10% V
CC
74F 10% V
CC
54F
74F
54F
74F
54F
74F
74F
74F
25
25
27
05
05
20 0
50
100
70
250
50
4 75
3 75
b
0 6
b
150
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CC
V
mA
mA
mA
V
mA
mA
mA
mA
Min
Max
Max
Max
00
00
Max
Max
Max
35
55
3
AC Electrical Characteristics
74F
Symbol
Parameter
Min
f
max
t
PLH
t
PHL
t
PHL
Maximum Clock Frequency
Propagation Delay
CP to Q
n
Propagation Delay
MR to Q
n
80
30
35
50
T
A
e a
25 C
V
CC
e a
5 0V
C
L
e
50 pF
Typ
120
48
50
70
75
80
10 0
Max
54F
T
A
V
CC
e
Mil
C
L
e
50 pF
Min
60
25
30
40
90
85
12 5
Max
74F
T
A
V
CC
e
Com
C
L
e
50 pF
Min
80
30
35
50
75
80
10 5
Max
MHz
ns
ns
Units
AC Operating Requirements
74F
Symbol
Parameter
T
A
e a
25 C
V
CC
e a
5 0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
rec
Setup Time HIGH or LOW
A or B to CP
Hold Time HIGH or LOW
A or B to CP
CP Pulse Width
HIGH or LOW
MR Pulse Width LOW
Recovery Time
MR to CP
45
40
10
10
40
70
40
50
Max
54F
T
A
V
CC
e
Mil
Min
55
40
10
10
40
70
50
65
Max
74F
T
A
V
CC
e
Com
Min
45
40
10
10
40
70
40
50
ns
ns
ns
Max
Units
ns
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74F
Temperature Range Family
74F
e
Commercial
54F
e
Military
Device Type
Package Code
P
e
Plastic DIP
D
e
Ceramic DIP
S
e
Small Outline Package SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
L
e
Package Leadless Chip Carrier (LCC)
F
e
Flatpak
164A
S
C
X
Special Variations
QB
e
Military grade device with
environmental and burn-in
processing
X
e
Devices shipped in 13 reel
Temperature Range
C
e
Commercial (0 C to
a
70 C)
M
e
Military (
b
55 C to
a
125 C)
4
Physical Dimensions
inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier Type C (L)
NS Package Number E20A
14-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J14A
5
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