NT68P81
USB Keyboard Micro-Controller
Features
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Built-in 6502C 8 -bit CPU
n
3 MHz CPU operation frequency when oscillator is
running at 6 MHz
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6K bytes of OTP (one time programming) ROM
n
256 bytes of SRAM
n
One 8-bit programmable base timer with pre-divider
circuit
n
29 programmable bi-directional I/O pins including two
external interrupts
n
n
n
n
n
n
n
n
n
3 LED direct sink pins with internal serial resistors
On-chip oscillator (Crystal or Ceramic Resonator)
Watch-dog timer reset
Built-in power-on reset
USB interface
3 supported endpoints
Remote wakeup provided
CMOS technology for low power consumption
40-pin DIP package, 42-pad Dice form and COB
General Description
The NT68P81 is a single chip micro-controller for USB
keyboard applications. It incorporates a 6502C 8
-bit
CPU core, 6K bytes of OTP ROM, and 256 bytes of RAM
used as working RAM and stack area. It also includes 29
programmable bi-directional I/O pins with built-in
resistors, and one 8-bit pre-loadable base timer.
Additionally, it includes a built-in power-on reset, a built-
in low voltage reset, an oscillator that requires crystal or
ceramic resonator applied, and a watch-dog timer that
prevents system standstill.
Pin Configuration
Pad Configuration
P
1
5
P
1
4
24
P
1
3
23
P
1
2
22
P
1
1
21
P
1
0
20
P
0
7
19
P
0
6
18
P
0
5
17
GND
VCP
VDP
VDM
[OE] P30
[PGM] P31
INT0/P32
INT1/P33
P34
[VPP] RESET
[A0] P00
[A1] P01
[A2] P02
[A3] P03
[A4] P04
[A5] P05
[A6] P06
[A7] P07
[A8] P10
[A9] P11
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
OSCI
OSCO
V
D D
LED2 [MODE2]
LED1 [MODE1]
LED0 [MODE0]
P27 [DB7]
P26 [DB6]
P25 [DB5]
P24 [DB4]
P23 [DB3]
P22 [DB2]
P21 [DB1]
P20 [DB0]
P17
P16
P15 [CE]
P14 [A12]
P13 [A11]
P12 [A10]
L
E
D
2
V
C
C
V
C
C
O
S
C
O
O
S
C
I
G
N
D
G
N
D
V
C
P
V
D
P
V
D
M
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
LED0
LED1
26
28
27
28
29
12
30
31
32
33
34
35
36
37
38
39
40
41
42
1
2
3
4
5
7
6
9
8
14
13
16
15
25
P04
P03
P02
P01
P00
RESET
P34
P33
P32
P31
P30
9
10
11
12
13
14
15
16
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
NT68P81
11
10
NT68P81
1
V2.0
NT68P81
Pin and Pad Descriptions
Pin No.
1
2
3
4
5
Pad No.
1,2
3
4
5
6
Designation
GND
VCP
VDP
VDM
P30
I/O
P
O
I/O
I/O
I/O
OE [I]
I/O
6
7
8
9
10
7
8
9
10
11
P31
PGM [I]
P32/INT0
P33/INT1
P34
RESET
Shared with OTP[I/O]
Ground
Description
USB 3.3V driver
USB data plus
USB data minus
Bi-directional I/O pin
Program output enable
Bi-directional I/O pin
Program control
Bi-directional I/O shared with INT0
Bi-directional I/O shared with INT1
Bi-directional I/O pin
Internally pulled down resistor
VPP [P]
Program supply voltage
Bi-directional I/O pin
A0 ~ A7 [I]
Program address buffer
Bi-directional I/O pin
A8 ~ A12
Program address buffer
Bi-directional I/O pin
CE [I]
Program chip enable
Bi-directional I/O pin
VPIH[I]
OTP Program Input Voltage High
Bi-directional I/O pin
Bi-directional I/O pin
DB0 ~ DB7 [I/O]
Program data buffer
LED direct sink
MODE0 [I]
Mode selection
LED direct sink
MODE1 [I]
Mode selection
LED direct sink
MODE2 [I]
Mode selection
Power supply (+5V)
Crystal oscillator output
CLK[I]
Program Clock
I/O
I/O
I/O
I
11 ~ 18
12 ~ 19
P00 ~ P07
I/O
19 ~ 23
20 ~ 24
P10 ~ P14
I/O
24
25
P15
I/O
25
26
27 ~ 34
26
27
28 ~ 35
P16
I/O
P17
P20 ~ P27
I/O
I/O
35
36
LED0
O
36
37
LED1
O
37
38
39
38
39,40
41
LED2
O
V
DD
OSCO
P
O
3
NT68P81
Functional Description
1. 6502C CPU
The 6502C is an 8 -bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true
indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory
range, and an interrupt input. Other features are also included.
The CPU clock cycle is 3MHz (6MHz system clock divided by 2). Please refer to 6502 data sheet for more detailed
information.
7
Accumulator A
7
Index Register Y
7
Index Register X
15
Program Counter PCH
PCL
7
7
Stack Pointer SP
7
N
V
B
D
I
Z
0
0
0
8
0
0
0
C
Status Register P
Carry
Zero
IRQ Disable
Decimal Mode
BRK Command
Overflow
Negative
1 = TRUE
1 = Result ZERO
1 = DISABLE
1 = TRUE
1 = BRK
1 = TRUE
1 = NEG
Figure 1. 6502 CPU Registers and Status Flags
5