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M74HCT74C1R

Description
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
Categorylogic    logic   
File Size235KB,11 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
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M74HCT74C1R Overview

DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR

M74HCT74C1R Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeQFN
package instructionPLASTIC, CC-20
Contacts20
Reach Compliance Codecompli
seriesHCT
JESD-30 codeS-PQCC-J20
JESD-609 codee3
length8.9662 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Su22000000 Hz
MaximumI(ol)0.004 A
Number of digits1
Number of functions2
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC20,.4SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
propagation delay (tpd)41 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width8.9662 mm
minfmax22 MHz
M54HCT74
M74HCT74
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
.
.
.
.
.
.
.
HIGH SPEED
f
MAX
= 53 MHz (TYP.) AT V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 2
µA
(MAX.) AT T
A
= 25
°C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS74
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
DESCRIPTION
The M54/74HCT74 is a high speed CMOS DUAL D
TYPE FLOP WITH PRESET AND CLEAR fabri-
cated in silicon gate C
2
MOS technology. It has the
same high speed performance of LSTTL combined
with true CMOS low power consumption. A signal on
the D INPUT is transferred to the Q OUTPUT during
the positive going transition of the clock pulse.
CLEAR and PRESET are independent of the clock
and accomplished by a low on the appropriate input.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age. This integrated circuit has input and output
characteristics that are fully compatible with 54/74
LSTTL logic families. M54/74HCT devices are de-
signed to directly interface HSC
2
MOS systems with
TTL and NMOS components. They are also plug in
replacements for LSTTL devices giving a reduction
of power consumption.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
ORDER CODES :
M54HCT74F1R
M74HCT74M1R
M74HCT74B1R
M74HCT74C1R
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
February 1993
1/11

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