570BIT datasheet, PDF - EEWORLD Datasheet

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570BIT: DescriptionClock Driver, 570 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8; Categorylogic logic; File Size250KB，11 Pages; ManufacturerIDT (Integrated Device Technology)

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570BIT Overview

Clock Driver, 570 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8

570BIT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
package instruction	SOIC-8
Contacts	8
Reach Compliance Code	not_compliant
ECCN code	EAR99
series	570
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.012 A
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	2
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.175 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
minfmax	170 MHz
Base Number Matches	1

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DATASHEET

MULTIPLIER AND ZERO DELAY BUFFER

Description

The ICS570 is a high-performance Zero Delay Buffer (ZDB)

which integrates IDT’s proprietary analog/digital Phase

Locked Loop (PLL) techniques. The A version is

recommended for 5 V designs and the B version for

3.3 V designs. The chip is part of IDT’s ClockBlocks

family, and was designed as a performance upgrade to

meet today’s higher speed and lower voltage requirements.

The zero delay feature means that the rising edge of the

input clock aligns with the rising edges of both output

clocks, giving the appearance of no delay through the

device. There are two outputs on the chip, one being a

low-skew divide by two of the other output. The device

incorporates an all-chip power down/tri-state mode that

stops the internal PLL and puts both outputs into a high

impedance state.

The ICS570 is ideal for synchronizing outputs in a large

variety of systems, from personal computers to data

communications to graphics/video. By allowing off-chip

feedback paths, the device can eliminate the delay through

other devices.

The ICS570 A and B versions were designed to improve

input to output jitter from the original ICS570M version, and

are recommended for all new designs.

ICS570

Features

•

8-pin SOIC package

Available in Pb (lead) free package

Pin-for-pin replacement and upgrade to ICS570M

Functional equivalent to AV9170 (not a pin-for-pin

replacement)

Low input to output skew of 300 ps max (>60 MHz

outputs)

Ability to choose between 14 different multipliers from

0.5x to 32x

Output clock frequency up to 170 MHz at 3.3 V

Can recover degraded input clock duty cycle

Output clock duty cycle of 45/55

Power Down and Tri-State Mode

Passes spread spectrum clock modulation

Full CMOS clock swings with 25 mA drive capability at

TTL levels

Advanced, low power CMOS process

ICS570B has an operating voltage of 3.3 V (±5%)

ICS570A has an operating voltage of 5.0 V (±5%)

Industrial temperature version available

Block Diagram

IC L K

S 1 :0

F B IN

d ivid e

by N

Phase

D e te c to r,

C h a rg e

Pum p,

and Loop

F ilte r

VCO

C LK

C LK2

E xte rn a l fe e d b a ck ca n co m e fro m C L K o r C L K /2 (se e ta b le o n p a g e 2 )

IDT™ / ICS™

MULTIPLIER AND ZERO DELAY BUFFER

ICS570

REV K 073007

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