M7010R-083ZA1T datasheet, PDF - EEWORLD Datasheet

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M7010R-083ZA1T: Description16K x 68-bit Entry NETWORK SEARCH ENGINE; CategoryWireless rf/communication Telecom circuit; File Size339KB，67 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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M7010R-083ZA1T Overview

16K x 68-bit Entry NETWORK SEARCH ENGINE

M7010R-083ZA1T Parametric

Parameter Name	Attribute value
Maker	STMicroelectronics
Parts packaging code	BGA
package instruction	27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272
Contacts	272
Reach Compliance Code	compli
JESD-30 code	S-PBGA-B272
length	27 mm
Number of functions	1
Number of terminals	272
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA272,20X20,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.8,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	2.6 mm
Nominal supply voltage	1.8 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	27 mm

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M7010R

16K x 68-bit Entry NETWORK SEARCH ENGINE

FEATURES SUMMARY

16K ENTRIES IN 68-BIT MODE

Figure 1. 272-ball PBGA Package

TABLE MAY BE PARTITIONED INTO UP TO

FOUR (4) QUADRANTS

(Data entry width in each quadrant is config-

urable as 34, 68, 136, or 272 bits.)

UP TO 83 MILLION SUSTAINED SEARCHES

PER SECOND IN 68-BIT and 136-BIT

CONFIGURATIONS

UP TO 41.5 MILLION SEARCHES PER

SECOND IN 34-BIT and 272-BIT

CONFIGURATIONS

SEARCHES ANY SUB-FIELD IN A SINGLE

CYCLE

OFFERS BIT-BY-BIT and GLOBAL MASKING

SYNCHRONOUS, PIPELINED OPERATION

UP TO 31 SEARCH ENGINES CASCADABLE

WITHOUT PERFORMANCE DEGRADATION

WHEN CASCADED, THE DATABASE

ENTRIES CAN SCALE FROM 124K to 992K

DEPENDING ON THE SIZE OF THE ENTRY

GLUELESS INTERFACE TO INDUSTRY-

STANDARD SRAMS

SIMPLE HARDWARE INSTRUCTION

INTERFACE

IEEE 1149.1 TEST ACCESS PORT

OPERATING SUPPLY VOLTAGES INCLUDE:

(Operating Supply Voltage) = 1.8V

DDQ

(Operating Supply Voltage for I/O) = 2.5

or 3.3V

272 BALL, 27mm x 27mm, CAVITY-UP BGA

272 PBGA

27mm x 27mm

1.27mm ball pitch

July 2002

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M7010R

TABLE OF CONTENTS

DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Product Range (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Switch/Router Implementation Using the M7010R (Figure 2.) . . . . .

Signal Names (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M7010R Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . .

.......

......

.....6

.....7

.....8

.....9

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Absolute Maximum Ratings (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DC and AC Measurement Conditions (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

M7010R 2.5V AC Testing Load (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

M7010R 2.5V Input Waveform (Figure 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

M7010R 2.5V Output Load Equiv. (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

M7010R 3.3V AC Testing Load (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

M7010R 3.3V Input Waveform (Figure 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

M7010R 3.3V Output Load Equiv. (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Capacitance (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

AC Timing Waveforms with CLK2X (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

AC Timing Parameters with CLK2X (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Command Bus and DQ Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Database Entry (Data Array and Mask Array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Arbitration Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pipeline and SRAM Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Full Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Connections Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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M7010R

CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Clocks (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Register Overview (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Comparand Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Comparand Register Selection During SEARCH and LEARN (Figure 13.). . . . . . . . . . . . . . . . . . . 19

Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Addressing the Global Mask Register (GMR) Array (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SEARCH-Successful Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SEARCH-Successful Register (SSR) Description (Table 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

The Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Command Register Field Descriptions (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SEARCH PROCEDURE FOR 32-BIT WIDE PREFIXES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Global Mask Register Patterns (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Storing left half of a Data or Mask Array (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

The Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Information Register Field Descriptions (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

The READ Burst Address Register (RBURREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

READ Burst Register Description (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

The WRITE Burst Address Register (WBURREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

WRITE Burst Register Description (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

The NFA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

NFA Register (Table 14.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SEARCH ENGINE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Data and Mask Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

M7010R Database Configuration (Figure 17.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Bit Position Match (Table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Multi-width Configuration Example (Figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

M7010R Data and Mask Array Addressing (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

COMMAND CODES AND PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Commands and Command Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Command Codes (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Command Parameters (Table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

READ COMMAND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Single Location READ Cycle Timing (Figure 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Burst READ of the Data and Mask Arrays (BLEN = 4) (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . 29

READ Command Parameters (Table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Data and Mask Array, SRAM READ Address Format (Table 19.) . . . . . . . . . . . . . . . . . . . . . . . . . 30

READ Address Format for Internal Registers (Table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

READ Address Format for Data and Mask Arrays (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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M7010R

WRITE COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Single Location WRITE Cycle Timing (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Burst WRITE of the Data and Mask Arrays (BLEN = 4) (Figure 23.). . . . . . . . . . . . . . . . . . . . . . . . 32

(Single) WRITE Address Format for Data and Mask Arrays or SRAM (Table 22.) . . . . . . . . . . . . . 33

WRITE Address Format for Internal Registers (Table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

WRITE Address Format for Data and Mask Array (Burst WRITE) (Table 24.) . . . . . . . . . . . . . . . . 33

SEARCH COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

68-bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Hardware Diagram for a Table with a Single Device (68-bit Operation) (Figure 24.) . . . . . . . . . . . 34

68-Bit Configuration SEARCH Timing Diagram (One Device) (Figure 25.). . . . . . . . . . . . . . . . . . . 35

Right-Shift of 68-bit Signals for TLSZ Values (Table 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Shift of SSF and SSV from SADR (for different HLAT Values) (Table 26.) . . . . . . . . . . . . . . . . . . . 36

Latency of SEARCH from Instruction to SRAM Access Cycle (68-bit Mode) (Table 27.) . . . . . . . . 36

68-bit Logical SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

x68 Table with One Device (Figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

136-bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Hardware Diagram for a Table with One Device (136-bit Operation) (Figure 27.) . . . . . . . . . . . . . 38

136-Bit Configuration SEARCH Timing Diagram (One Device) (Figure 28.). . . . . . . . . . . . . . . . . . 39

Right-Shift of 136-bit Signals for TLSZ Values (Table 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Shift of SSF and SSV from SADR (for different HLAT values) (Table 29.) . . . . . . . . . . . . . . . . . . . 40

Latency of SEARCH from Instruction to SRAM Access Cycle (136-bit Mode) (Table 30.) . . . . . . . 40

136-bit Logical SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

x136 Table with One Device (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

272-bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Hardware Diagram for a Table with One Device (272-bit Operation) (Figure 30.) . . . . . . . . . . . . . 42

272-Bit Configuration SEARCH Timing Diagram (One Device) (Figure 31.). . . . . . . . . . . . . . . . . . 43

Right-Shift of 272-bit Signals for TLSZ Values (Table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Shift of SSF and SSV from SADR (for different HLAT Values) (Table 32.) . . . . . . . . . . . . . . . . . . . 44

Latency of SEARCH from Instruction to SRAM Access Cycle (272-bit Mode) (Table 33.) . . . . . . . 44

272-bit Logical SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

x272 Table with One Device (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Mixed-sized Searches on Tables Configured with Different Width Using an M7010R Device 46

Multiwidth Configuration Example (Figure 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Timing Diagram for Mixed SEARCH (One Device) (Figure 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

LRAM and LDEV Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

LEARN COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

LEARN Command Timing Diagram (TLSZ = 00) (Figure 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

LEARN Timing Diagram (TLSZ = 1, except on Last Device) (Figure 36.) . . . . . . . . . . . . . . . . . . . . 50

LEARN Timing Diagram on Device Number 7 (TLSZ = 01) (Figure 37.). . . . . . . . . . . . . . . . . . . . . 51

SRAM WRITE Cycle Latency from Second Cycle of LEARN Instruction (Table 34.) . . . . . . . . . . . 51

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M7010R

DEPTH-CASCADING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Depth-Cascading Up to Eight Devices (One Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Depth-Cascading Up to 31 Devices (4 Blocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Depth-Cascading to Generate a “FULL” State for a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Depth-Cascading to Form a Single Block (8 Devices) (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . . . . 53

Four Blocks (31 Devices Cascaded) SEARCH, 68-bit Configured with LDEV = 1 (Figure 39.) . . . 54

“FULL” State Generation in a Cascaded Table (Figure 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Timing Diagram for Arbitration Within a Block (Figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Timing for Arbitration for Two or More Blocks for the Last Device (Figure 42.). . . . . . . . . . . . . . . . 57

SRAM ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

SRAM PIO Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

SRAM READ Access for One M7010R Device (Figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

SRAM WRITE Access for One M7010R Device (Figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

SRAM Bus Address Generation (Table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Right-Shift of SRAM Signals for TLSZ Values (Table 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Right-Shift of SRAM Signals for HLAT Values (Table 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

JTAG (1149.1) TESTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Test Access Port Controller Instructions (Table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

TAP Device ID Register (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

POWER DISTRIBUTION GUIDELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Network Search Engine Power Distribution (Figure 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

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M7010R-083ZA1T Related Products

	M7010R-083ZA1T	M7010R	M7010R-066ZA1T
Description	16K x 68-bit Entry NETWORK SEARCH ENGINE	16K x 68-bit Entry NETWORK SEARCH ENGINE	16K x 68-bit Entry NETWORK SEARCH ENGINE
Maker	STMicroelectronics	-	STMicroelectronics
Parts packaging code	BGA	-	BGA
package instruction	27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272	-	27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272
Contacts	272	-	272
Reach Compliance Code	compli	-	compli
JESD-30 code	S-PBGA-B272	-	S-PBGA-B272
length	27 mm	-	27 mm
Number of functions	1	-	1
Number of terminals	272	-	272
Maximum operating temperature	70 °C	-	70 °C
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	BGA	-	BGA
Encapsulate equivalent code	BGA272,20X20,50	-	BGA272,20X20,50
Package shape	SQUARE	-	SQUARE
Package form	GRID ARRAY	-	GRID ARRAY
power supply	1.8,2.5/3.3 V	-	1.8,2.5/3.3 V
Certification status	Not Qualified	-	Not Qualified
Maximum seat height	2.6 mm	-	2.6 mm
Nominal supply voltage	1.8 V	-	1.8 V
surface mount	YES	-	YES
Telecom integrated circuit types	TELECOM CIRCUIT	-	TELECOM CIRCUIT
Temperature level	COMMERCIAL	-	COMMERCIAL
Terminal form	BALL	-	BALL
Terminal pitch	1.27 mm	-	1.27 mm
Terminal location	BOTTOM	-	BOTTOM
width	27 mm	-	27 mm

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