Am49LV128BM
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
31022
Revision
A
Amendment
+5
Issue Date
March 15, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am49LV128BM
Stacked Multi-Chip Package (MCP)
128 Megabit (8 M x 16-Bit) MirrorBit™ Uniform Sector Flash Memory and
32 Mbit (2 M x 16-Bit) pseudo-static RAM with Page Mode
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
Single power supply operation
— 3 volt read, erase, and program operations
Manufactured on 0.23 µm MirrorBit process
technology
SecSi™ (Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number,
accessible through a command sequence
— May be programmed and locked by the customer
Flexible sector architecture
— Two hundred fifty-six 32 Kword sectors
Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
Minimum 100,000 erase cycle guarantee per sector
20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
High performance
— As fast as 105 ns access time
— 25 ns page read times
— 0.5 s typical sector erase time
— 15 µs typical write buffer word programming time: 16-
word write buffer reduces overall programming time
for multiple-word updates
— 4-word page read buffer
— 16-word write buffer
Low power consumption (typical values at 3.0 V, 5
MHz)
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
Package option
— 64-ball FBGA
SOFTWARE & HARDWARE FEATURES
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word or byte programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Group Unprotect: V
ID
-level method
of changing code in locked sector groups
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects last sector
regardless of sector protection settings
— Hardware reset input (RESET#) resets device
PSRAM FEATURES
Asynchronous SRAM Interface
Fast Access Time
— t
CE
= t
AA
= 65 ns max
Low Voltage Operating Condition
— V
DD
= 2.7 to + 3.1 V
Byte Control by LB# and UB#
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication Number:
31022
Rev:
A
Amendment:+5
Issue Date:
March 15, 2004
A D V A N C E
I N F O R M A T I O N
S U P P L E M E N T
GENERAL DESCRIPTION
The 128 Mbit MirrorBit device is a 128 Mbit, 3.0 volt
single power supply flash memory devices organized
as 8,388,608 words. The device has a 16-bit wide data
bus. The device can be programmed either in the host
system or in standard EPROM programmers.
An access time of 105 or 110 ns is available. Each de-
vice has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 volt power
supply
for both read and write functions. In addition to
a V
CC
input, a high-voltage
accelerated program
(WP#/ACC)
input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle)
status bits
to de-
termine whether the operation is complete. To facilitate
programming, an
Unlock Bypass
mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature allows
the host system to pause an erase operation in a
given sector group to read or program any other sector
group and then complete the erase operation. The
Program Suspend/Program Resume
feature en-
ables the host system to pause a program operation in
a given sector group to read any other sector group
and then complete the program operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power consumption in the
standby mode
when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The
SecSi™ (Secured Silicon) Sector
provides a
128-word area for code or data that can be perma-
nently protected. Once this sector is protected, no fur-
ther changes within the sector can occur.
The
Write Protect (WP#/ACC)
feature protects the
last sector by asserting a logic low on the WP# pin.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
RELATED DOCUMENTS
For a comprehensive information on MirrorBit prod-
ucts, including migration information, data sheets, ap-
plication notes, and software drivers, please see
www.amd.com
→
Flash Memory
→
Product Informa-
tion
→
MirrorBit
→
Flash Information
→
Technical Docu-
mentation.
The following is a partial list of documents
closely related to this product:
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
Migrating from Single-byte to Three-byte Device IDs
2
Am49LV128BM
March 15, 2004
A D V A N C E
I N F O R M A T I O N
S U P P L E M E N T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Special Package Handling Instructions .................................... 6
Look Ahead pinout . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations ..................................................... 10
DQ2: Toggle Bit II ................................................................... 34
Reading Toggle Bits DQ6/DQ2 ............................................... 35
DQ5: Exceeded Timing Limits ................................................ 35
DQ3: Sector Erase Timer ....................................................... 35
DQ1: Write-to-Buffer Abort ..................................................... 35
Table 10. Write Operation Status................................................... 36
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 37
Figure 9. Maximum Negative Overshoot
Waveform ....................................................................................... 37
Figure 10. Maximum Positive Overshoo
Waveform ....................................................................................... 37
Requirements for Reading Array Data ................................... 10
Page Mode Read ............................................................................11
Writing Commands/Command Sequences ............................ 11
Write Buffer .....................................................................................11
Accelerated Program Operation ......................................................11
Autoselect Functions .......................................................................11
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 37
Flash DC Characteristics . . . . . . . . . . . . . . . . . . . 38
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Test Setup .................................................................... 39
Table 11. Test Specifications ......................................................... 39
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 12
VCC Power-up and Power-down Sequencing ................................12
Key to Switching Waveforms. . . . . . . . . . . . . . . . 39
Figure 12. Input Waveforms and
Measurement Levels ...................................................................... 39
Output Disable Mode .............................................................. 12
Table 2. Sector Address Table........................................................ 12
SecSi (Secured Silicon) Sector Flash Memory
Region .................................................................................... 17
Table 3. SecSi Sector Contents ...................................................... 18
Table 4. Sector Group Protection/Unprotection Address
Table .............................................................................................. 19
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40
VCC Power-up ........................................................................ 40
Figure 13. V
CC
Power-up Diagram ................................................ 40
Figure 14. Read Operations Timings ............................................. 41
Figure 15. Page Read Timings ...................................................... 42
Hardware Reset (RESET#) .................................................... 43
Figure 16. Reset Timings ............................................................... 43
Temporary Sector Group Unprotect ....................................... 20
Figure 1. Temporary Sector Group Unprotect
Operation ........................................................................................20
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...21
Erase and Program Operations .............................................. 44
Figure 17. Program Operation Timings .......................................... 45
Figure 18. Accelerated Program Timing Diagram .......................... 45
Figure 19. Chip/Sector Erase Operation Timings .......................... 46
Figure 20. Data# Polling Timings (During Embedded
Algorithms) ..................................................................................... 47
Figure 21. Toggle Bit Timings (During Embedded
Algorithms) ..................................................................................... 48
Figure 22. DQ2 vs. DQ6 ................................................................. 48
Hardware Data Protection ...................................................... 22
Low VCC Write Inhibit .....................................................................22
Write Pulse “Glitch” Protection ........................................................22
Logical Inhibit ..................................................................................22
Power-Up Write Inhibit ....................................................................22
Common Flash Memory Interface (CFI) . . . . . . . 22
Command Definitions . . . . . . . . . . . . . . . . . . . . . 24
Reading Array Data ................................................................ 24
Reset Command ..................................................................... 25
Autoselect Command Sequence ............................................ 25
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25
Word Program Command Sequence ..................................... 25
Unlock Bypass Command Sequence ..............................................26
Write Buffer Programming ...............................................................26
Accelerated Program ......................................................................27
Figure 3. Write Buffer Programming Operation ...............................28
Figure 4. Program Operation ..........................................................29
Temporary Sector Unprotect .................................................. 49
Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 49
Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 50
Alternate CE# Controlled Erase and Program
Operations .............................................................................. 51
Figure 25. Alternate CE# Controlled Write (Erase/
Program) Operation Timings ......................................................... 52
Program Suspend/Program Resume Command
Sequence ............................................................................... 29
Figure 5. Program Suspend/Program Resume ...............................30
Chip Erase Command Sequence ........................................... 30
Sector Erase Command Sequence ........................................ 30
Figure 6. Erase Operation ...............................................................31
Latchup Characteristics . . . . . . . . . . . . . . . . . . . .
Erase And Programming Performance. . . . . . . .
BGA Package Capacitance . . . . . . . . . . . . . . . . .
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Am49LV128BM Mcp with Standard Supplier . . .
pSRAM Block Diagram . . . . . . . . . . . . . . . . . . . . .
Function Truth Table . . . . . . . . . . . . . . . . . . . . . .
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
53
53
53
54
54
55
56
Erase Suspend/Erase Resume Commands ........................... 31
Write Operation Status . . . . . . . . . . . . . . . . . . . . 33
DQ7: Data# Polling ................................................................. 33
Figure 7. Data# Polling Algorithm ...................................................33
Power Down ................................................................................... 56
Power Down Program Sequence ................................................... 56
Address Key ................................................................................... 56
DQ6: Toggle Bit I .................................................................... 33
Figure 8. Toggle Bit Algorithm .........................................................34
Recommended Operating Conditions . . . . . . . . 57
pSRAM DC Characteristics . . . . . . . . . . . . . . . . . 58
pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 59
Read Operation ...................................................................... 59
Write Operation ....................................................................... 60
March 15, 2004
Am49LV128BM
3
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
