Multiplexer allows one of 2 inputs to be selected onto
one output pin and the 1:2 MUX switches one input to
one of two outputs. This device is useful for multiplexing multi-
rate Ethernet PHYs which have 100M bit and 1000M bit
transmit/receive pairs onto an optical SFP module which has
a single transmit/receive pair. See Application Section for
further information.
F
EATURES
•
Four banks of three LVDS outputs
•
Twelve differential data inputs
•
Serial I
2
C Interface
•
Data pairs can accept the following differential input levels:
LVPECL, LVDS, CML
•
Maximum output frequency: 1.3GHz
•
Part-to-part skew: TBD
•
Propagation delay: 675ps (tyical)
•
Full 3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
The ICS854S54I-08 is optimiz ed for ATCA backplane
swtich applications requiring very high performance and has a
maximum operating frequency of 1.3GHz. The device is
packaged in a small, 10mm x 10mm TQFP package, making it
ideal for use on space-constrained boards.
P
IN
A
SSIGNMENT
nINC0
nINA1
nINA0
nINC1
SCLK
INC0
INC1
nINB
INA1
INA0
INB
QA0
nQA0
GND
QA1
nQA1
V
DD
QB
nQB
nQF
QF
V
DD
nQE1
QE1
GND
nQE0
QE0
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
DD
nIND
GND
SDA
IND
QC0
nQC0
GND
QC1
nQC1
V
DD
QD
nQD
nQH
QH
V
DD
nQG1
QG1
GND
nQG0
QG0
ICS854S54I-08
64-Lead TQFP E-Pad
10mm x 10mm x 1.0mm
package body
Y package
Top View
10
11
12
13
14
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
INE1
nINE1
nINE0
INE0
nINF
INF
V
DD
ADR1
ADR0
GND
ING0
ING1
nING0
nING1
INH
nINH
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
LVDS MULTIPLEXER
1
ICS854S54AYI-08 REV B JANUARY 16, 2008
ICS854S54I-08
OCTAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
PRELIMINARY
B
LOCK
D
IAGRAM
INB
nINB
INA0
nINA0
1
0
0
QA0
nQA0
INA1
nINA1
0
QB
nQB
1
QA1
nQA1
1
SEL_QB MODE_QAx
IND
nIND
SDA
SCL
ADR[1:0]
INC0
nINC0
1
0
0
2
QC0
nQC0
INC1
nINC1
0
I
2
C
QD
nQD
1
QC1
nQC1
1
SEL_QD MODE_QCx
INF
nIF
INE0
nINE0
1
0
0
QE0
nQE0
INE1
nINE1
0
QF
nQF
1
QE1
nQE1
1
SEL_QF MODE_QEx
INH
nINH
ING0
nING0
1
0
0
QG0
nQG0
ING1
nING1
0
QH
nQH
1
QG1
nQG1
1
SEL_QH MODE_QGx
IDT
™
/ ICS
™
LVDS MULTIPLEXER
2
ICS854S54AYI-08 REV B JANUARY 16, 2008
ICS854S54I-08
OCTAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
PRELIMINARY
I
2
C C
ONTROL
D
ESCRIPTION
The ICS854S54I-08 uses an industry standard I
2
C interface
to control the direction of the 4 separate 2:1/1:2 mux switch
blocks. Each individual block is controlled by two bits of the 8
bit Data Byte. The Data Byte bit pairs are summarized as fol-
lows:
C
ONTROL
S
IGNALS
Bit Pair 1
– INA0/nINA0, INA1/nINA1, INB/nINB, QB/nQB
SEL_QB:MODE_QAx
Bit Pair 2
- INC0/nINC0, INC1/nINC1, IND/nIND, QD/nQD
SEL_QD:MODE_QCx
C
ONTROL
S
IGNALS
Bit Pair 3
– INE0/nINE0, INE1/nINE1, INF/nINF, QF/nQF
SEL_QF:MODE_QEx
Bit Pair 4
– ING0/nING0, ING1/nING1, INH/nINH, QH/nQH
SEL_QH:MODE_QGx
Data Byte 0
Bit 7
Control Bit
Power-up
Default Value
MODE_QGx
1
Bit 6
SEL_QH
0
Bit 5
MODE_QEx
1
Bit 4
SEL_QF
0
Bit 3
MODE_QCx
1
Bit 2
SEL_QD
0
Bit 1
MODE_QAx
1
Bit 0
SEL_QB
0
I
2
C A
DDRESSING
The ICS854S54I-08 can be set to decode one of four addresses
to minimize the chance of address conflict on the I
2
C bus. The
ADR_SEL (pins 24 & 25) = Default (1, 1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
1
0
1
1
1
1
address that is decoded is controlled by the setting of the ADR_1,
ADR_0 (pins 24 and 25).
Bit 7
1
Bit 0
R/W
Bit 7
1
Bit 6
1
ADR_SEL (pins 24 & 25) = (1, 0)
Bit 5
Bit 4
Bit 3
Bit 2
0
1
1
1
Bit 1
0
Bit 0
R/W
Bit 7
1
ADR_SEL (pins 24 & 25) = Default (0, 1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
1
0
1
1
0
1
Bit 0
R/W
Bit 7
1
Bit 6
1
ADR_SEL (pins 24 & 25) = (0, 0)
Bit 5
Bit 4
Bit 3
Bit 2
0
1
1
0
Bit 1
0
Bit 0
R/ W
IDT
™
/ ICS
™
LVDS MULTIPLEXER
3
ICS854S54AYI-08 REV B JANUARY 16, 2008
ICS854S54I-08
OCTAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
PRELIMINARY
S
ERIAL
I
NTERFACE
- P
ROTOCOL
The ICS854S54I-08 is a slave-only device and uses the standard
I
2
C protocol as shown in the below diagrams. The maximum SCLK
frequency is greater than 400kHz which is more than sufficient for
standard I
2
C clock speeds.
SCLK
SDATA
START
Valid Data
Acknowledge
STOP
START (ST)
– defined as high-to-low transition on SDATA while holding SCLK HIGH.
DATA
- Between START and STOP cycles, SDATA is synchronous with SCLK.
Data may change only when SCLK is LOW and must be stable when SCLK is HIGH.
ACKNOWLEDGE (AK)
– SDATA is driven LOW before the SCLK rising edge and
held LOW until the SCLK falling edge.
STOP (SP)
– defined as low-to-high transition on SDATA while holding SCLK HIGH.
S
ERIAL
I
NTERFACE
- A W
RITE
E
XAMPLE
A serial transfer to the ICS854S54I-08 always consists of an
address cycle followed by a single data byte. Any additional data
bytes will not be acknowledged and the ICS854S54I-08 will leave
the data bus HIGH. These extra bits will not be loaded into the
serial control register. Once the Data Byte is loaded and the master
generates a stop condition, the values in the serial control register
are latched into the mux control bit outputs and each mux will
switch into the new state.
ST
1 Bit
Slave Address: 7 Bits
Refer to page 3 for address choices based on ADDR_SEL pin setting
R/W
1 Bit
AK
1 Bit
Data Byte 0: 8 Bits
MODE_QGx
SEL_QH
MODE_QEx
SEL_QF
MODE_QCx
SEL_QD
MODE_QAx
SEL_QB
AK
1 Bi t
SP
1 Bit
IDT
™
/ ICS
™
LVDS MULTIPLEXER
4
ICS854S54AYI-08 REV B JANUARY 16, 2008
ICS854S54I-08
OCTAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
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